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dc98e4145d
This patch moves header files from plat-s3c24xx to plat-samsung to remove plat-s3c24xx directory to make one plat-samsung directory for Samsung SoCs. And this patch includes fixing coding style, too. Cc: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
152 lines
6.0 KiB
C
152 lines
6.0 KiB
C
/* arch/arm/plat-samsung/include/plat/regs-udc.h
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*
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* Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
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*
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* This include file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#ifndef __ASM_ARCH_REGS_UDC_H
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#define __ASM_ARCH_REGS_UDC_H
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#define S3C2410_USBDREG(x) (x)
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#define S3C2410_UDC_FUNC_ADDR_REG S3C2410_USBDREG(0x0140)
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#define S3C2410_UDC_PWR_REG S3C2410_USBDREG(0x0144)
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#define S3C2410_UDC_EP_INT_REG S3C2410_USBDREG(0x0148)
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#define S3C2410_UDC_USB_INT_REG S3C2410_USBDREG(0x0158)
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#define S3C2410_UDC_EP_INT_EN_REG S3C2410_USBDREG(0x015c)
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#define S3C2410_UDC_USB_INT_EN_REG S3C2410_USBDREG(0x016c)
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#define S3C2410_UDC_FRAME_NUM1_REG S3C2410_USBDREG(0x0170)
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#define S3C2410_UDC_FRAME_NUM2_REG S3C2410_USBDREG(0x0174)
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#define S3C2410_UDC_EP0_FIFO_REG S3C2410_USBDREG(0x01c0)
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#define S3C2410_UDC_EP1_FIFO_REG S3C2410_USBDREG(0x01c4)
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#define S3C2410_UDC_EP2_FIFO_REG S3C2410_USBDREG(0x01c8)
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#define S3C2410_UDC_EP3_FIFO_REG S3C2410_USBDREG(0x01cc)
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#define S3C2410_UDC_EP4_FIFO_REG S3C2410_USBDREG(0x01d0)
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#define S3C2410_UDC_EP1_DMA_CON S3C2410_USBDREG(0x0200)
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#define S3C2410_UDC_EP1_DMA_UNIT S3C2410_USBDREG(0x0204)
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#define S3C2410_UDC_EP1_DMA_FIFO S3C2410_USBDREG(0x0208)
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#define S3C2410_UDC_EP1_DMA_TTC_L S3C2410_USBDREG(0x020c)
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#define S3C2410_UDC_EP1_DMA_TTC_M S3C2410_USBDREG(0x0210)
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#define S3C2410_UDC_EP1_DMA_TTC_H S3C2410_USBDREG(0x0214)
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#define S3C2410_UDC_EP2_DMA_CON S3C2410_USBDREG(0x0218)
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#define S3C2410_UDC_EP2_DMA_UNIT S3C2410_USBDREG(0x021c)
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#define S3C2410_UDC_EP2_DMA_FIFO S3C2410_USBDREG(0x0220)
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#define S3C2410_UDC_EP2_DMA_TTC_L S3C2410_USBDREG(0x0224)
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#define S3C2410_UDC_EP2_DMA_TTC_M S3C2410_USBDREG(0x0228)
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#define S3C2410_UDC_EP2_DMA_TTC_H S3C2410_USBDREG(0x022c)
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#define S3C2410_UDC_EP3_DMA_CON S3C2410_USBDREG(0x0240)
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#define S3C2410_UDC_EP3_DMA_UNIT S3C2410_USBDREG(0x0244)
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#define S3C2410_UDC_EP3_DMA_FIFO S3C2410_USBDREG(0x0248)
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#define S3C2410_UDC_EP3_DMA_TTC_L S3C2410_USBDREG(0x024c)
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#define S3C2410_UDC_EP3_DMA_TTC_M S3C2410_USBDREG(0x0250)
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#define S3C2410_UDC_EP3_DMA_TTC_H S3C2410_USBDREG(0x0254)
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#define S3C2410_UDC_EP4_DMA_CON S3C2410_USBDREG(0x0258)
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#define S3C2410_UDC_EP4_DMA_UNIT S3C2410_USBDREG(0x025c)
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#define S3C2410_UDC_EP4_DMA_FIFO S3C2410_USBDREG(0x0260)
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#define S3C2410_UDC_EP4_DMA_TTC_L S3C2410_USBDREG(0x0264)
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#define S3C2410_UDC_EP4_DMA_TTC_M S3C2410_USBDREG(0x0268)
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#define S3C2410_UDC_EP4_DMA_TTC_H S3C2410_USBDREG(0x026c)
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#define S3C2410_UDC_INDEX_REG S3C2410_USBDREG(0x0178)
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/* indexed registers */
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#define S3C2410_UDC_MAXP_REG S3C2410_USBDREG(0x0180)
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#define S3C2410_UDC_EP0_CSR_REG S3C2410_USBDREG(0x0184)
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#define S3C2410_UDC_IN_CSR1_REG S3C2410_USBDREG(0x0184)
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#define S3C2410_UDC_IN_CSR2_REG S3C2410_USBDREG(0x0188)
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#define S3C2410_UDC_OUT_CSR1_REG S3C2410_USBDREG(0x0190)
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#define S3C2410_UDC_OUT_CSR2_REG S3C2410_USBDREG(0x0194)
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#define S3C2410_UDC_OUT_FIFO_CNT1_REG S3C2410_USBDREG(0x0198)
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#define S3C2410_UDC_OUT_FIFO_CNT2_REG S3C2410_USBDREG(0x019c)
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#define S3C2410_UDC_FUNCADDR_UPDATE (1 << 7)
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#define S3C2410_UDC_PWR_ISOUP (1 << 7) /* R/W */
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#define S3C2410_UDC_PWR_RESET (1 << 3) /* R */
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#define S3C2410_UDC_PWR_RESUME (1 << 2) /* R/W */
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#define S3C2410_UDC_PWR_SUSPEND (1 << 1) /* R */
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#define S3C2410_UDC_PWR_ENSUSPEND (1 << 0) /* R/W */
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#define S3C2410_UDC_PWR_DEFAULT (0x00)
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#define S3C2410_UDC_INT_EP4 (1 << 4) /* R/W (clear only) */
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#define S3C2410_UDC_INT_EP3 (1 << 3) /* R/W (clear only) */
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#define S3C2410_UDC_INT_EP2 (1 << 2) /* R/W (clear only) */
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#define S3C2410_UDC_INT_EP1 (1 << 1) /* R/W (clear only) */
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#define S3C2410_UDC_INT_EP0 (1 << 0) /* R/W (clear only) */
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#define S3C2410_UDC_USBINT_RESET (1 << 2) /* R/W (clear only) */
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#define S3C2410_UDC_USBINT_RESUME (1 << 1) /* R/W (clear only) */
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#define S3C2410_UDC_USBINT_SUSPEND (1 << 0) /* R/W (clear only) */
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#define S3C2410_UDC_INTE_EP4 (1 << 4) /* R/W */
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#define S3C2410_UDC_INTE_EP3 (1 << 3) /* R/W */
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#define S3C2410_UDC_INTE_EP2 (1 << 2) /* R/W */
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#define S3C2410_UDC_INTE_EP1 (1 << 1) /* R/W */
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#define S3C2410_UDC_INTE_EP0 (1 << 0) /* R/W */
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#define S3C2410_UDC_USBINTE_RESET (1 << 2) /* R/W */
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#define S3C2410_UDC_USBINTE_SUSPEND (1 << 0) /* R/W */
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#define S3C2410_UDC_INDEX_EP0 (0x00)
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#define S3C2410_UDC_INDEX_EP1 (0x01)
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#define S3C2410_UDC_INDEX_EP2 (0x02)
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#define S3C2410_UDC_INDEX_EP3 (0x03)
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#define S3C2410_UDC_INDEX_EP4 (0x04)
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#define S3C2410_UDC_ICSR1_CLRDT (1 << 6) /* R/W */
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#define S3C2410_UDC_ICSR1_SENTSTL (1 << 5) /* R/W (clear only) */
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#define S3C2410_UDC_ICSR1_SENDSTL (1 << 4) /* R/W */
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#define S3C2410_UDC_ICSR1_FFLUSH (1 << 3) /* W (set only) */
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#define S3C2410_UDC_ICSR1_UNDRUN (1 << 2) /* R/W (clear only) */
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#define S3C2410_UDC_ICSR1_PKTRDY (1 << 0) /* R/W (set only) */
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#define S3C2410_UDC_ICSR2_AUTOSET (1 << 7) /* R/W */
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#define S3C2410_UDC_ICSR2_ISO (1 << 6) /* R/W */
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#define S3C2410_UDC_ICSR2_MODEIN (1 << 5) /* R/W */
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#define S3C2410_UDC_ICSR2_DMAIEN (1 << 4) /* R/W */
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#define S3C2410_UDC_OCSR1_CLRDT (1 << 7) /* R/W */
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#define S3C2410_UDC_OCSR1_SENTSTL (1 << 6) /* R/W (clear only) */
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#define S3C2410_UDC_OCSR1_SENDSTL (1 << 5) /* R/W */
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#define S3C2410_UDC_OCSR1_FFLUSH (1 << 4) /* R/W */
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#define S3C2410_UDC_OCSR1_DERROR (1 << 3) /* R */
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#define S3C2410_UDC_OCSR1_OVRRUN (1 << 2) /* R/W (clear only) */
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#define S3C2410_UDC_OCSR1_PKTRDY (1 << 0) /* R/W (clear only) */
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#define S3C2410_UDC_OCSR2_AUTOCLR (1 << 7) /* R/W */
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#define S3C2410_UDC_OCSR2_ISO (1 << 6) /* R/W */
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#define S3C2410_UDC_OCSR2_DMAIEN (1 << 5) /* R/W */
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#define S3C2410_UDC_EP0_CSR_OPKRDY (1 << 0)
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#define S3C2410_UDC_EP0_CSR_IPKRDY (1 << 1)
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#define S3C2410_UDC_EP0_CSR_SENTSTL (1 << 2)
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#define S3C2410_UDC_EP0_CSR_DE (1 << 3)
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#define S3C2410_UDC_EP0_CSR_SE (1 << 4)
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#define S3C2410_UDC_EP0_CSR_SENDSTL (1 << 5)
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#define S3C2410_UDC_EP0_CSR_SOPKTRDY (1 << 6)
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#define S3C2410_UDC_EP0_CSR_SSE (1 << 7)
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#define S3C2410_UDC_MAXP_8 (1 << 0)
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#define S3C2410_UDC_MAXP_16 (1 << 1)
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#define S3C2410_UDC_MAXP_32 (1 << 2)
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#define S3C2410_UDC_MAXP_64 (1 << 3)
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#endif
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