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https://github.com/edk2-porting/linux-next.git
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5c44778eb0
This patch adds s3c_fb_driverdata s3c_fb_data_exynos5 for EXYNOS5 and adds extended timing control setting. EXYNOS5 FIMD needs extended setting for video timing control. Additional bits are added to VIDTCON2, VIDWxxADD2, VIDOSDxA and VIDOSDxB registers in order to set timing value for lager resolution. Also, address offset of VIDTCONx registers is changed from 0x0 to 0x20000, thus variable type should be changed to int type to handle the address offset of VIDTCONx registers for EXYNOS5 FIMD. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
404 lines
14 KiB
C
404 lines
14 KiB
C
/* arch/arm/plat-samsung/include/plat/regs-fb.h
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C Platform - new-style framebuffer register definitions
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*
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* This is the register set for the new style framebuffer interface
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* found from the S3C2443 onwards into the S3C2416, S3C2450 and the
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* S3C64XX series such as the S3C6400 and S3C6410.
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*
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* The file does not contain the cpu specific items which are based on
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* whichever architecture is selected, it only contains the core of the
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* register set. See <mach/regs-fb.h> to get the specifics.
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*
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* Note, we changed to using regs-fb.h as it avoids any clashes with
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* the original regs-lcd.h so out of the way of regs-lcd.h as well as
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* indicating the newer block is much more than just an LCD interface.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/* Please do not include this file directly, use <mach/regs-fb.h> to
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* ensure all the localised SoC support is included as necessary.
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*/
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/* VIDCON0 */
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#define VIDCON0 (0x00)
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#define VIDCON0_INTERLACE (1 << 29)
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#define VIDCON0_VIDOUT_MASK (0x3 << 26)
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#define VIDCON0_VIDOUT_SHIFT (26)
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#define VIDCON0_VIDOUT_RGB (0x0 << 26)
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#define VIDCON0_VIDOUT_TV (0x1 << 26)
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#define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
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#define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
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#define VIDCON0_L1_DATA_MASK (0x7 << 23)
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#define VIDCON0_L1_DATA_SHIFT (23)
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#define VIDCON0_L1_DATA_16BPP (0x0 << 23)
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#define VIDCON0_L1_DATA_18BPP16 (0x1 << 23)
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#define VIDCON0_L1_DATA_18BPP9 (0x2 << 23)
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#define VIDCON0_L1_DATA_24BPP (0x3 << 23)
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#define VIDCON0_L1_DATA_18BPP (0x4 << 23)
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#define VIDCON0_L1_DATA_16BPP8 (0x5 << 23)
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#define VIDCON0_L0_DATA_MASK (0x7 << 20)
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#define VIDCON0_L0_DATA_SHIFT (20)
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#define VIDCON0_L0_DATA_16BPP (0x0 << 20)
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#define VIDCON0_L0_DATA_18BPP16 (0x1 << 20)
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#define VIDCON0_L0_DATA_18BPP9 (0x2 << 20)
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#define VIDCON0_L0_DATA_24BPP (0x3 << 20)
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#define VIDCON0_L0_DATA_18BPP (0x4 << 20)
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#define VIDCON0_L0_DATA_16BPP8 (0x5 << 20)
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#define VIDCON0_PNRMODE_MASK (0x3 << 17)
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#define VIDCON0_PNRMODE_SHIFT (17)
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#define VIDCON0_PNRMODE_RGB (0x0 << 17)
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#define VIDCON0_PNRMODE_BGR (0x1 << 17)
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#define VIDCON0_PNRMODE_SERIAL_RGB (0x2 << 17)
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#define VIDCON0_PNRMODE_SERIAL_BGR (0x3 << 17)
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#define VIDCON0_CLKVALUP (1 << 16)
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#define VIDCON0_CLKVAL_F_MASK (0xff << 6)
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#define VIDCON0_CLKVAL_F_SHIFT (6)
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#define VIDCON0_CLKVAL_F_LIMIT (0xff)
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#define VIDCON0_CLKVAL_F(_x) ((_x) << 6)
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#define VIDCON0_VLCKFREE (1 << 5)
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#define VIDCON0_CLKDIR (1 << 4)
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#define VIDCON0_CLKSEL_MASK (0x3 << 2)
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#define VIDCON0_CLKSEL_SHIFT (2)
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#define VIDCON0_CLKSEL_HCLK (0x0 << 2)
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#define VIDCON0_CLKSEL_LCD (0x1 << 2)
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#define VIDCON0_CLKSEL_27M (0x3 << 2)
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#define VIDCON0_ENVID (1 << 1)
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#define VIDCON0_ENVID_F (1 << 0)
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#define VIDCON1 (0x04)
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#define VIDCON1_LINECNT_MASK (0x7ff << 16)
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#define VIDCON1_LINECNT_SHIFT (16)
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#define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff)
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#define VIDCON1_VSTATUS_MASK (0x3 << 13)
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#define VIDCON1_VSTATUS_SHIFT (13)
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#define VIDCON1_VSTATUS_VSYNC (0x0 << 13)
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#define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13)
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#define VIDCON1_VSTATUS_ACTIVE (0x2 << 13)
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#define VIDCON1_VSTATUS_FRONTPORCH (0x0 << 13)
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#define VIDCON1_VCLK_MASK (0x3 << 9)
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#define VIDCON1_VCLK_HOLD (0x0 << 9)
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#define VIDCON1_VCLK_RUN (0x1 << 9)
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#define VIDCON1_INV_VCLK (1 << 7)
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#define VIDCON1_INV_HSYNC (1 << 6)
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#define VIDCON1_INV_VSYNC (1 << 5)
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#define VIDCON1_INV_VDEN (1 << 4)
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/* VIDCON2 */
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#define VIDCON2 (0x08)
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#define VIDCON2_EN601 (1 << 23)
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#define VIDCON2_TVFMTSEL_SW (1 << 14)
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#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
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#define VIDCON2_TVFMTSEL1_SHIFT (12)
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#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
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#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
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#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
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#define VIDCON2_ORGYCbCr (1 << 8)
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#define VIDCON2_YUVORDCrCb (1 << 7)
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/* PRTCON (S3C6410, S5PC100)
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* Might not be present in the S3C6410 documentation,
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* but tests prove it's there almost for sure; shouldn't hurt in any case.
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*/
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#define PRTCON (0x0c)
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#define PRTCON_PROTECT (1 << 11)
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/* VIDTCON0 */
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#define VIDTCON0_VBPDE_MASK (0xff << 24)
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#define VIDTCON0_VBPDE_SHIFT (24)
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#define VIDTCON0_VBPDE_LIMIT (0xff)
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#define VIDTCON0_VBPDE(_x) ((_x) << 24)
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#define VIDTCON0_VBPD_MASK (0xff << 16)
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#define VIDTCON0_VBPD_SHIFT (16)
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#define VIDTCON0_VBPD_LIMIT (0xff)
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#define VIDTCON0_VBPD(_x) ((_x) << 16)
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#define VIDTCON0_VFPD_MASK (0xff << 8)
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#define VIDTCON0_VFPD_SHIFT (8)
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#define VIDTCON0_VFPD_LIMIT (0xff)
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#define VIDTCON0_VFPD(_x) ((_x) << 8)
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#define VIDTCON0_VSPW_MASK (0xff << 0)
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#define VIDTCON0_VSPW_SHIFT (0)
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#define VIDTCON0_VSPW_LIMIT (0xff)
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#define VIDTCON0_VSPW(_x) ((_x) << 0)
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/* VIDTCON1 */
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#define VIDTCON1_VFPDE_MASK (0xff << 24)
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#define VIDTCON1_VFPDE_SHIFT (24)
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#define VIDTCON1_VFPDE_LIMIT (0xff)
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#define VIDTCON1_VFPDE(_x) ((_x) << 24)
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#define VIDTCON1_HBPD_MASK (0xff << 16)
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#define VIDTCON1_HBPD_SHIFT (16)
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#define VIDTCON1_HBPD_LIMIT (0xff)
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#define VIDTCON1_HBPD(_x) ((_x) << 16)
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#define VIDTCON1_HFPD_MASK (0xff << 8)
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#define VIDTCON1_HFPD_SHIFT (8)
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#define VIDTCON1_HFPD_LIMIT (0xff)
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#define VIDTCON1_HFPD(_x) ((_x) << 8)
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#define VIDTCON1_HSPW_MASK (0xff << 0)
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#define VIDTCON1_HSPW_SHIFT (0)
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#define VIDTCON1_HSPW_LIMIT (0xff)
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#define VIDTCON1_HSPW(_x) ((_x) << 0)
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#define VIDTCON2 (0x18)
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#define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23)
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#define VIDTCON2_LINEVAL_MASK (0x7ff << 11)
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#define VIDTCON2_LINEVAL_SHIFT (11)
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#define VIDTCON2_LINEVAL_LIMIT (0x7ff)
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#define VIDTCON2_LINEVAL(_x) (((_x) & 0x7ff) << 11)
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#define VIDTCON2_HOZVAL_E(_x) ((((_x) & 0x800) >> 11) << 22)
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#define VIDTCON2_HOZVAL_MASK (0x7ff << 0)
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#define VIDTCON2_HOZVAL_SHIFT (0)
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#define VIDTCON2_HOZVAL_LIMIT (0x7ff)
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#define VIDTCON2_HOZVAL(_x) (((_x) & 0x7ff) << 0)
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/* WINCONx */
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#define WINCONx_BITSWP (1 << 18)
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#define WINCONx_BYTSWP (1 << 17)
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#define WINCONx_HAWSWP (1 << 16)
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#define WINCONx_WSWP (1 << 15)
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#define WINCONx_BURSTLEN_MASK (0x3 << 9)
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#define WINCONx_BURSTLEN_SHIFT (9)
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#define WINCONx_BURSTLEN_16WORD (0x0 << 9)
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#define WINCONx_BURSTLEN_8WORD (0x1 << 9)
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#define WINCONx_BURSTLEN_4WORD (0x2 << 9)
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#define WINCONx_ENWIN (1 << 0)
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#define WINCON0_BPPMODE_MASK (0xf << 2)
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#define WINCON0_BPPMODE_SHIFT (2)
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#define WINCON0_BPPMODE_1BPP (0x0 << 2)
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#define WINCON0_BPPMODE_2BPP (0x1 << 2)
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#define WINCON0_BPPMODE_4BPP (0x2 << 2)
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#define WINCON0_BPPMODE_8BPP_PALETTE (0x3 << 2)
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#define WINCON0_BPPMODE_16BPP_565 (0x5 << 2)
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#define WINCON0_BPPMODE_16BPP_1555 (0x7 << 2)
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#define WINCON0_BPPMODE_18BPP_666 (0x8 << 2)
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#define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
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#define WINCON1_BLD_PIX (1 << 6)
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#define WINCON1_ALPHA_SEL (1 << 1)
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#define WINCON1_BPPMODE_MASK (0xf << 2)
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#define WINCON1_BPPMODE_SHIFT (2)
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#define WINCON1_BPPMODE_1BPP (0x0 << 2)
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#define WINCON1_BPPMODE_2BPP (0x1 << 2)
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#define WINCON1_BPPMODE_4BPP (0x2 << 2)
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#define WINCON1_BPPMODE_8BPP_PALETTE (0x3 << 2)
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#define WINCON1_BPPMODE_8BPP_1232 (0x4 << 2)
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#define WINCON1_BPPMODE_16BPP_565 (0x5 << 2)
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#define WINCON1_BPPMODE_16BPP_A1555 (0x6 << 2)
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#define WINCON1_BPPMODE_16BPP_I1555 (0x7 << 2)
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#define WINCON1_BPPMODE_18BPP_666 (0x8 << 2)
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#define WINCON1_BPPMODE_18BPP_A1665 (0x9 << 2)
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#define WINCON1_BPPMODE_19BPP_A1666 (0xa << 2)
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#define WINCON1_BPPMODE_24BPP_888 (0xb << 2)
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#define WINCON1_BPPMODE_24BPP_A1887 (0xc << 2)
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#define WINCON1_BPPMODE_25BPP_A1888 (0xd << 2)
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#define WINCON1_BPPMODE_28BPP_A4888 (0xd << 2)
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/* S5PV210 */
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#define SHADOWCON (0x34)
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#define SHADOWCON_WINx_PROTECT(_win) (1 << (10 + (_win)))
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/* DMA channels (all windows) */
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#define SHADOWCON_CHx_ENABLE(_win) (1 << (_win))
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/* Local input channels (windows 0-2) */
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#define SHADOWCON_CHx_LOCAL_ENABLE(_win) (1 << (5 + (_win)))
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#define VIDOSDxA_TOPLEFT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)
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#define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11)
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#define VIDOSDxA_TOPLEFT_X_SHIFT (11)
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#define VIDOSDxA_TOPLEFT_X_LIMIT (0x7ff)
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#define VIDOSDxA_TOPLEFT_X(_x) (((_x) & 0x7ff) << 11)
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#define VIDOSDxA_TOPLEFT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)
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#define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0)
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#define VIDOSDxA_TOPLEFT_Y_SHIFT (0)
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#define VIDOSDxA_TOPLEFT_Y_LIMIT (0x7ff)
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#define VIDOSDxA_TOPLEFT_Y(_x) (((_x) & 0x7ff) << 0)
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#define VIDOSDxB_BOTRIGHT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)
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#define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11)
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#define VIDOSDxB_BOTRIGHT_X_SHIFT (11)
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#define VIDOSDxB_BOTRIGHT_X_LIMIT (0x7ff)
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#define VIDOSDxB_BOTRIGHT_X(_x) (((_x) & 0x7ff) << 11)
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#define VIDOSDxB_BOTRIGHT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)
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#define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0)
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#define VIDOSDxB_BOTRIGHT_Y_SHIFT (0)
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#define VIDOSDxB_BOTRIGHT_Y_LIMIT (0x7ff)
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#define VIDOSDxB_BOTRIGHT_Y(_x) (((_x) & 0x7ff) << 0)
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/* For VIDOSD[1..4]C */
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#define VIDISD14C_ALPHA0_R(_x) ((_x) << 20)
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#define VIDISD14C_ALPHA0_G_MASK (0xf << 16)
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#define VIDISD14C_ALPHA0_G_SHIFT (16)
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#define VIDISD14C_ALPHA0_G_LIMIT (0xf)
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#define VIDISD14C_ALPHA0_G(_x) ((_x) << 16)
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#define VIDISD14C_ALPHA0_B_MASK (0xf << 12)
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#define VIDISD14C_ALPHA0_B_SHIFT (12)
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#define VIDISD14C_ALPHA0_B_LIMIT (0xf)
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#define VIDISD14C_ALPHA0_B(_x) ((_x) << 12)
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#define VIDISD14C_ALPHA1_R_MASK (0xf << 8)
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#define VIDISD14C_ALPHA1_R_SHIFT (8)
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#define VIDISD14C_ALPHA1_R_LIMIT (0xf)
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#define VIDISD14C_ALPHA1_R(_x) ((_x) << 8)
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#define VIDISD14C_ALPHA1_G_MASK (0xf << 4)
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#define VIDISD14C_ALPHA1_G_SHIFT (4)
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#define VIDISD14C_ALPHA1_G_LIMIT (0xf)
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#define VIDISD14C_ALPHA1_G(_x) ((_x) << 4)
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#define VIDISD14C_ALPHA1_B_MASK (0xf << 0)
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#define VIDISD14C_ALPHA1_B_SHIFT (0)
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#define VIDISD14C_ALPHA1_B_LIMIT (0xf)
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#define VIDISD14C_ALPHA1_B(_x) ((_x) << 0)
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/* Video buffer addresses */
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#define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8))
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#define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8))
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#define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8))
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#define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8))
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#define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4))
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#define VIDW_BUF_SIZE_OFFSET_E(_x) ((((_x) & 0x2000) >> 13) << 27)
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#define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13)
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#define VIDW_BUF_SIZE_OFFSET_SHIFT (13)
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#define VIDW_BUF_SIZE_OFFSET_LIMIT (0x1fff)
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#define VIDW_BUF_SIZE_OFFSET(_x) (((_x) & 0x1fff) << 13)
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#define VIDW_BUF_SIZE_PAGEWIDTH_E(_x) ((((_x) & 0x2000) >> 13) << 26)
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#define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff << 0)
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#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT (0)
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#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT (0x1fff)
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#define VIDW_BUF_SIZE_PAGEWIDTH(_x) (((_x) & 0x1fff) << 0)
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/* Interrupt controls and status */
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#define VIDINTCON0_FIFOINTERVAL_MASK (0x3f << 20)
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#define VIDINTCON0_FIFOINTERVAL_SHIFT (20)
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#define VIDINTCON0_FIFOINTERVAL_LIMIT (0x3f)
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#define VIDINTCON0_FIFOINTERVAL(_x) ((_x) << 20)
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#define VIDINTCON0_INT_SYSMAINCON (1 << 19)
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#define VIDINTCON0_INT_SYSSUBCON (1 << 18)
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#define VIDINTCON0_INT_I80IFDONE (1 << 17)
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#define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15)
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#define VIDINTCON0_FRAMESEL0_SHIFT (15)
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#define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15)
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#define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15)
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#define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15)
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#define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15)
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#define VIDINTCON0_FRAMESEL1 (1 << 13)
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#define VIDINTCON0_FRAMESEL1_MASK (0x3 << 13)
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#define VIDINTCON0_FRAMESEL1_NONE (0x0 << 13)
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#define VIDINTCON0_FRAMESEL1_BACKPORCH (0x1 << 13)
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#define VIDINTCON0_FRAMESEL1_VSYNC (0x2 << 13)
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#define VIDINTCON0_FRAMESEL1_FRONTPORCH (0x3 << 13)
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#define VIDINTCON0_INT_FRAME (1 << 12)
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#define VIDINTCON0_FIFIOSEL_MASK (0x7f << 5)
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#define VIDINTCON0_FIFIOSEL_SHIFT (5)
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#define VIDINTCON0_FIFIOSEL_WINDOW0 (0x1 << 5)
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#define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5)
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#define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 2)
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#define VIDINTCON0_FIFOLEVEL_SHIFT (2)
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#define VIDINTCON0_FIFOLEVEL_TO25PC (0x0 << 2)
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#define VIDINTCON0_FIFOLEVEL_TO50PC (0x1 << 2)
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#define VIDINTCON0_FIFOLEVEL_TO75PC (0x2 << 2)
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#define VIDINTCON0_FIFOLEVEL_EMPTY (0x3 << 2)
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#define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 2)
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#define VIDINTCON0_INT_FIFO_MASK (0x3 << 0)
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#define VIDINTCON0_INT_FIFO_SHIFT (0)
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#define VIDINTCON0_INT_ENABLE (1 << 0)
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#define VIDINTCON1 (0x134)
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#define VIDINTCON1_INT_I180 (1 << 2)
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#define VIDINTCON1_INT_FRAME (1 << 1)
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#define VIDINTCON1_INT_FIFO (1 << 0)
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/* Window colour-key control registers */
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#define WKEYCON (0x140) /* 6410,V210 */
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#define WKEYCON0 (0x00)
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#define WKEYCON1 (0x04)
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#define WxKEYCON0_KEYBL_EN (1 << 26)
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#define WxKEYCON0_KEYEN_F (1 << 25)
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#define WxKEYCON0_DIRCON (1 << 24)
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#define WxKEYCON0_COMPKEY_MASK (0xffffff << 0)
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#define WxKEYCON0_COMPKEY_SHIFT (0)
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#define WxKEYCON0_COMPKEY_LIMIT (0xffffff)
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#define WxKEYCON0_COMPKEY(_x) ((_x) << 0)
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#define WxKEYCON1_COLVAL_MASK (0xffffff << 0)
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#define WxKEYCON1_COLVAL_SHIFT (0)
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#define WxKEYCON1_COLVAL_LIMIT (0xffffff)
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#define WxKEYCON1_COLVAL(_x) ((_x) << 0)
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/* Window blanking (MAP) */
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#define WINxMAP_MAP (1 << 24)
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#define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0)
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#define WINxMAP_MAP_COLOUR_SHIFT (0)
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#define WINxMAP_MAP_COLOUR_LIMIT (0xffffff)
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#define WINxMAP_MAP_COLOUR(_x) ((_x) << 0)
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#define WPALCON_PAL_UPDATE (1 << 9)
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#define WPALCON_W1PAL_MASK (0x7 << 3)
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#define WPALCON_W1PAL_SHIFT (3)
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#define WPALCON_W1PAL_25BPP_A888 (0x0 << 3)
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#define WPALCON_W1PAL_24BPP (0x1 << 3)
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#define WPALCON_W1PAL_19BPP_A666 (0x2 << 3)
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#define WPALCON_W1PAL_18BPP_A665 (0x3 << 3)
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#define WPALCON_W1PAL_18BPP (0x4 << 3)
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#define WPALCON_W1PAL_16BPP_A555 (0x5 << 3)
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#define WPALCON_W1PAL_16BPP_565 (0x6 << 3)
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#define WPALCON_W0PAL_MASK (0x7 << 0)
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#define WPALCON_W0PAL_SHIFT (0)
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#define WPALCON_W0PAL_25BPP_A888 (0x0 << 0)
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#define WPALCON_W0PAL_24BPP (0x1 << 0)
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#define WPALCON_W0PAL_19BPP_A666 (0x2 << 0)
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#define WPALCON_W0PAL_18BPP_A665 (0x3 << 0)
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#define WPALCON_W0PAL_18BPP (0x4 << 0)
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#define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
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#define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
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/* Blending equation control */
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#define BLENDCON (0x260)
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#define BLENDCON_NEW_MASK (1 << 0)
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#define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
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#define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
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