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2c6db77c02
The correct name of the third clock is hda2codec_2x. Signed-off-by: Dylan Reid <dgreid@chromium.org> Signed-off-by: Takashi Iwai <tiwai@suse.de>
29 lines
1.1 KiB
Plaintext
29 lines
1.1 KiB
Plaintext
NVIDIA Tegra30 HDA controller
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Required properties:
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- compatible : "nvidia,tegra30-hda"
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- reg : Should contain the HDA registers location and length.
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- interrupts : The interrupt from the HDA controller.
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- clocks : Must contain an entry for each required entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names : Must include the following entries: hda, hdacodec_2x, hda2hdmi
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- resets : Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names : Must include the following entries: hda, hdacodec_2x, hda2hdmi
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Example:
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hda@0,70030000 {
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compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
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reg = <0x0 0x70030000 0x0 0x10000>;
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interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_HDA>,
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<&tegra_car TEGRA124_CLK_HDA2HDMI>,
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<&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
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clock-names = "hda", "hda2hdmi", "hda2codec_2x";
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resets = <&tegra_car 125>, /* hda */
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<&tegra_car 128>; /* hda2hdmi */
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<&tegra_car 111>, /* hda2codec_2x */
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reset-names = "hda", "hda2hdmi", "hda2codec_2x";
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};
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