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18f48a4f1d
NVIDIA Tegra124 supports has the new GPIO port as GPIO_FF. Add the macro for this port name. Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
52 lines
1.4 KiB
C
52 lines
1.4 KiB
C
/*
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* This header provides constants for binding nvidia,tegra*-gpio.
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*
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* The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
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* provide names for this.
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*
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* The second cell contains standard flag values specified in gpio.h.
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*/
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#ifndef _DT_BINDINGS_GPIO_TEGRA_GPIO_H
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#define _DT_BINDINGS_GPIO_TEGRA_GPIO_H
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#include <dt-bindings/gpio/gpio.h>
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#define TEGRA_GPIO_BANK_ID_A 0
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#define TEGRA_GPIO_BANK_ID_B 1
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#define TEGRA_GPIO_BANK_ID_C 2
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#define TEGRA_GPIO_BANK_ID_D 3
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#define TEGRA_GPIO_BANK_ID_E 4
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#define TEGRA_GPIO_BANK_ID_F 5
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#define TEGRA_GPIO_BANK_ID_G 6
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#define TEGRA_GPIO_BANK_ID_H 7
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#define TEGRA_GPIO_BANK_ID_I 8
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#define TEGRA_GPIO_BANK_ID_J 9
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#define TEGRA_GPIO_BANK_ID_K 10
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#define TEGRA_GPIO_BANK_ID_L 11
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#define TEGRA_GPIO_BANK_ID_M 12
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#define TEGRA_GPIO_BANK_ID_N 13
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#define TEGRA_GPIO_BANK_ID_O 14
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#define TEGRA_GPIO_BANK_ID_P 15
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#define TEGRA_GPIO_BANK_ID_Q 16
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#define TEGRA_GPIO_BANK_ID_R 17
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#define TEGRA_GPIO_BANK_ID_S 18
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#define TEGRA_GPIO_BANK_ID_T 19
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#define TEGRA_GPIO_BANK_ID_U 20
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#define TEGRA_GPIO_BANK_ID_V 21
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#define TEGRA_GPIO_BANK_ID_W 22
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#define TEGRA_GPIO_BANK_ID_X 23
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#define TEGRA_GPIO_BANK_ID_Y 24
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#define TEGRA_GPIO_BANK_ID_Z 25
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#define TEGRA_GPIO_BANK_ID_AA 26
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#define TEGRA_GPIO_BANK_ID_BB 27
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#define TEGRA_GPIO_BANK_ID_CC 28
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#define TEGRA_GPIO_BANK_ID_DD 29
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#define TEGRA_GPIO_BANK_ID_EE 30
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#define TEGRA_GPIO_BANK_ID_FF 31
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#define TEGRA_GPIO(bank, offset) \
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((TEGRA_GPIO_BANK_ID_##bank * 8) + offset)
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#endif
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