Russell King 2c4133c5d0 ARM: l2c: zynq: remove cache size override ... The cache size should already be present in the L2 cache auxiliary control register: it is part of the integration process to configure the hardware IP. Most platforms get this right, yet still many cargo-cult program, and assume that they always need specifying to the L2 cache code. Remove them so we can find out which really need this. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>		2014-05-30 00:50:28 +01:00
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common.c	ARM: l2c: zynq: remove cache size override	2014-05-30 00:50:28 +01:00
common.h	ARM: zynq: Make zynq_slcr_base static	2014-02-10 11:21:19 +01:00
headsmp.S	arm: zynq: Invalidate L1 in secondary boot	2013-12-10 14:17:55 +01:00
hotplug.c	arm: zynq: hotplug: Remove unreachable code	2013-08-20 07:32:13 +02:00
Kconfig	ARM: SoC: late cleanups	2014-04-05 15:46:37 -07:00
Makefile	arm: zynq: Add hotplug support	2013-04-04 09:24:00 +02:00
Makefile.boot	ARM: 7022/1: allow to detect conflicting zreladdrs	2011-10-17 09:12:40 +01:00
platsmp.c	ARM: zynq: remove unnecessary setting of cpu_present_mask	2013-12-10 14:20:25 +01:00
slcr.c	ARM: zynq: Introduce zynq_slcr_unlock()	2014-02-10 11:21:45 +01:00