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mirror of https://github.com/edk2-porting/linux-next.git synced 2025-01-11 23:23:52 +08:00
linux-next/drivers/clk/sunxi-ng
Jernej Skrabec 2abc330c51
clk: sunxi-ng: nkmp: Avoid GENMASK(-1, 0)
Sometimes one of the nkmp factors is unused. This means that one of the
factors shift and width values are set to 0. Current nkmp clock code
generates a mask for each factor with GENMASK(width + shift - 1, shift).
For unused factor this translates to GENMASK(-1, 0). This code is
further expanded by C preprocessor to final version:
(((~0UL) - (1UL << (0)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (-1))))
or a bit simplified:
(~0UL & (~0UL >> BITS_PER_LONG))

It turns out that result of the second part (~0UL >> BITS_PER_LONG) is
actually undefined by C standard, which clearly specifies:

"If the value of the right operand is negative or is greater than or
equal to the width of the promoted left operand, the behavior is
undefined."

Additionally, compiling kernel with aarch64-linux-gnu-gcc 8.3.0 gave
different results whether literals or variables with same values as
literals were used. GENMASK with literals -1 and 0 gives zero and with
variables gives 0xFFFFFFFFFFFFFFF (~0UL). Because nkmp driver uses
GENMASK with variables as parameter, expression calculates mask as ~0UL
instead of 0. This has further consequences that LSB in register is
always set to 1 (1 is neutral value for a factor and shift is 0).

For example, H6 pll-de clock is set to 600 MHz by sun4i-drm driver, but
due to this bug ends up being 300 MHz. Additionally, 300 MHz seems to be
too low because following warning can be found in dmesg:

[    1.752763] WARNING: CPU: 2 PID: 41 at drivers/clk/sunxi-ng/ccu_common.c:41 ccu_helper_wait_for_lock.part.0+0x6c/0x90
[    1.763378] Modules linked in:
[    1.766441] CPU: 2 PID: 41 Comm: kworker/2:1 Not tainted 5.1.0-rc2-next-20190401 #138
[    1.774269] Hardware name: Pine H64 (DT)
[    1.778200] Workqueue: events deferred_probe_work_func
[    1.783341] pstate: 40000005 (nZcv daif -PAN -UAO)
[    1.788135] pc : ccu_helper_wait_for_lock.part.0+0x6c/0x90
[    1.793623] lr : ccu_helper_wait_for_lock.part.0+0x48/0x90
[    1.799107] sp : ffff000010f93840
[    1.802422] x29: ffff000010f93840 x28: 0000000000000000
[    1.807735] x27: ffff800073ce9d80 x26: ffff000010afd1b8
[    1.813049] x25: ffffffffffffffff x24: 00000000ffffffff
[    1.818362] x23: 0000000000000001 x22: ffff000010abd5c8
[    1.823675] x21: 0000000010000000 x20: 00000000685f367e
[    1.828987] x19: 0000000000001801 x18: 0000000000000001
[    1.834300] x17: 0000000000000001 x16: 0000000000000000
[    1.839613] x15: 0000000000000000 x14: ffff000010789858
[    1.844926] x13: 0000000000000000 x12: 0000000000000001
[    1.850239] x11: 0000000000000000 x10: 0000000000000970
[    1.855551] x9 : ffff000010f936c0 x8 : ffff800074cec0d0
[    1.860864] x7 : 0000800067117000 x6 : 0000000115c30b41
[    1.866177] x5 : 00ffffffffffffff x4 : 002c959300bfe500
[    1.871490] x3 : 0000000000000018 x2 : 0000000029aaaaab
[    1.876802] x1 : 00000000000002e6 x0 : 00000000686072bc
[    1.882114] Call trace:
[    1.884565]  ccu_helper_wait_for_lock.part.0+0x6c/0x90
[    1.889705]  ccu_helper_wait_for_lock+0x10/0x20
[    1.894236]  ccu_nkmp_set_rate+0x244/0x2a8
[    1.898334]  clk_change_rate+0x144/0x290
[    1.902258]  clk_core_set_rate_nolock+0x180/0x1b8
[    1.906963]  clk_set_rate+0x34/0xa0
[    1.910455]  sun8i_mixer_bind+0x484/0x558
[    1.914466]  component_bind_all+0x10c/0x230
[    1.918651]  sun4i_drv_bind+0xc4/0x1a0
[    1.922401]  try_to_bring_up_master+0x164/0x1c0
[    1.926932]  __component_add+0xa0/0x168
[    1.930769]  component_add+0x10/0x18
[    1.934346]  sun8i_dw_hdmi_probe+0x18/0x20
[    1.938443]  platform_drv_probe+0x50/0xa0
[    1.942455]  really_probe+0xcc/0x280
[    1.946032]  driver_probe_device+0x54/0xe8
[    1.950130]  __device_attach_driver+0x80/0xb8
[    1.954488]  bus_for_each_drv+0x78/0xc8
[    1.958326]  __device_attach+0xd4/0x130
[    1.962163]  device_initial_probe+0x10/0x18
[    1.966348]  bus_probe_device+0x90/0x98
[    1.970185]  deferred_probe_work_func+0x6c/0xa0
[    1.974720]  process_one_work+0x1e0/0x320
[    1.978732]  worker_thread+0x228/0x428
[    1.982484]  kthread+0x120/0x128
[    1.985714]  ret_from_fork+0x10/0x18
[    1.989290] ---[ end trace 9babd42e1ca4b84f ]---

This commit solves the issue by first checking value of the factor
width. If it is equal to 0 (unused factor), mask is set to 0, otherwise
GENMASK() macro is used as before.

Fixes: d897ef56fa ("clk: sunxi-ng: Mask nkmp factors when setting register")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-03 09:53:04 +02:00
..
ccu_common.c Allwinner clock patches for 4.12 2017-04-19 09:02:00 -07:00
ccu_common.h clk: move clock common macros out from vendor directories 2017-12-21 15:00:38 -08:00
ccu_div.c clk: divider: fix incorrect usage of container_of 2017-12-28 15:16:04 -08:00
ccu_div.h clk: sunxi-ng: div: Add support for fixed post-divider 2017-08-14 22:31:46 +08:00
ccu_frac.c clk: sunxi-ng: Wait for lock when using fractional mode 2017-08-01 10:18:23 +08:00
ccu_frac.h clk: sunxi-ng: Wait for lock when using fractional mode 2017-08-01 10:18:23 +08:00
ccu_gate.c clk: sunxi-ng: gate: Support common pre-dividers 2017-03-06 10:25:56 +01:00
ccu_gate.h clk: sunxi-ng: Add gate clock support 2016-07-08 18:04:38 -07:00
ccu_mmc_timing.c clk: sunxi-ng: Add interface to query or configure MMC timing modes. 2017-08-30 14:01:47 +02:00
ccu_mp.c clk: sunxi-ng: Adjust MP clock parent rate when allowed 2018-11-05 10:21:01 +01:00
ccu_mp.h clk: sunxi-ng: Support fixed post-dividers on MP style clocks 2017-12-07 10:09:44 +01:00
ccu_mult.c clk: sunxi-ng: Wait for lock when using fractional mode 2017-08-01 10:18:23 +08:00
ccu_mult.h License cleanup: add SPDX GPL-2.0 license identifier to files with no license 2017-11-02 11:10:55 +01:00
ccu_mux.c clk: sunxi-ng: Staticize ccu_mux_helper_unapply_prediv() 2017-06-16 14:51:36 -07:00
ccu_mux.h License cleanup: add SPDX GPL-2.0 license identifier to files with no license 2017-11-02 11:10:55 +01:00
ccu_nk.c clk: sunxi-ng: use 1 as fallback for minimum multiplier 2017-04-13 14:09:25 +02:00
ccu_nk.h clk: sunxi-ng: Rename the internal structures 2016-10-20 19:24:20 +02:00
ccu_nkm.c clk: sunxi-ng: nkm: add support for fixed post-divider 2017-08-14 22:45:06 +08:00
ccu_nkm.h clk: sunxi-ng: nkm: add support for fixed post-divider 2017-08-14 22:45:06 +08:00
ccu_nkmp.c clk: sunxi-ng: nkmp: Avoid GENMASK(-1, 0) 2019-04-03 09:53:04 +02:00
ccu_nkmp.h clk: sunxi-ng: nkmp: Add constraint for maximum rate 2018-08-27 09:18:10 +02:00
ccu_nm.c clk: sunxi-ng: Use u64 for calculation of NM rate 2018-11-05 10:21:29 +01:00
ccu_nm.h clk: sunxi-ng: Add maximum rate constraint to NM PLLs 2018-08-27 09:18:01 +02:00
ccu_phase.c clk: sunxi-ng: Add phase clock support 2016-07-08 18:04:45 -07:00
ccu_phase.h clk: sunxi-ng: Add phase clock support 2016-07-08 18:04:45 -07:00
ccu_reset.c clk: sunxi-ng: Implement reset control status readback 2017-09-26 11:13:03 +02:00
ccu_reset.h clk: sunxi-ng: explicitly include linux/spinlock.h 2017-06-07 15:32:12 +02:00
ccu_sdm.c clk: sunxi-ng: Add sigma-delta modulation support 2017-10-13 09:27:06 +02:00
ccu_sdm.h clk: sunxi-ng: Add sigma-delta modulation support 2017-10-13 09:27:06 +02:00
ccu-sun4i-a10.c clk: sunxi-ng: sun4i: Set VCO and PLL bias current to lowest setting 2018-09-07 10:20:50 +02:00
ccu-sun4i-a10.h clk: sunxi-ng: sun4i: Export video PLLs 2017-10-17 19:32:16 +02:00
ccu-sun5i.c clk: sunxi-ng: sun5i: Use sigma-delta modulation for audio PLL 2017-10-13 09:27:29 +02:00
ccu-sun5i.h clk: sunxi-ng: sun5i: Export video PLLs 2017-06-07 15:32:14 +02:00
ccu-sun6i-a31.c clk: sunxi: A31: Fix wrong AHB gate number 2019-01-28 09:26:32 +01:00
ccu-sun6i-a31.h clk: sunxi-ng: sun6i: Export video PLLs 2017-09-29 10:46:10 +02:00
ccu-sun8i-a23-a33.h clk: sunxi-ng: Add A33 CCU support 2016-09-10 11:41:19 +02:00
ccu-sun8i-a23.c clk: sunxi-ng: sun8i-a23: Enable PLL-MIPI LDOs when ungating it 2019-01-25 10:43:44 +01:00
ccu-sun8i-a33.c clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for all audio module clocks 2018-12-05 12:08:20 +01:00
ccu-sun8i-a83t.c clk: sunxi-ng: a83t: Add max. rate constraint to video PLLs 2018-08-27 09:18:11 +02:00
ccu-sun8i-a83t.h clk: sunxi-ng: Add driver for A83T CCU 2017-06-07 15:32:16 +02:00
ccu-sun8i-de2.c clk: sunxi-ng: Add support for H6 DE3 clocks 2018-11-05 10:22:50 +01:00
ccu-sun8i-de2.h clk: sunxi-ng: Add support for H6 DE3 clocks 2018-11-05 10:22:50 +01:00
ccu-sun8i-h3.c clk: sunxi-ng: h3: Allow parent change for ve clock 2018-12-04 08:43:58 +01:00
ccu-sun8i-h3.h clk: sunxi-ng: h3: h5: export CLK_PLL_VIDEO 2018-03-02 08:42:30 +01:00
ccu-sun8i-r40.c clk: sunxi-ng: r40: Force LOSC parent to RTC LOSC output 2018-11-30 11:54:39 +08:00
ccu-sun8i-r40.h clk: sunxi-ng: r40: Export video PLLs 2018-06-27 19:06:56 +02:00
ccu-sun8i-r.c clk: Convert to using %pOF instead of full_name 2017-07-21 15:49:54 -07:00
ccu-sun8i-r.h clk: sunxi-ng: Fix header guard of ccu-sun8i-r.h 2017-07-27 16:53:47 +02:00
ccu-sun8i-v3s.c clk: sunxi-ng: v3s: Fix TCON reset de-assert bit 2019-01-22 10:03:04 +01:00
ccu-sun8i-v3s.h clk: sunxi-ng: add support for V3s CCU 2017-01-20 21:39:03 +01:00
ccu-sun9i-a80-de.c clk: sunxi-ng: sun9i-a80: Fix wrong pointer passed to PTR_ERR() 2017-02-06 15:01:29 -08:00
ccu-sun9i-a80-de.h clk: sunxi-ng: Add A80 Display Engine CCU 2017-01-30 08:38:30 +01:00
ccu-sun9i-a80-usb.c clk: sunxi-ng: Add A80 USB CCU 2017-01-30 08:37:51 +01:00
ccu-sun9i-a80-usb.h clk: sunxi-ng: Add A80 USB CCU 2017-01-30 08:37:51 +01:00
ccu-sun9i-a80.c clk: sunxi-ng: a80: Fix audio PLL comment not matching actual code 2017-04-13 14:09:30 +02:00
ccu-sun9i-a80.h clk: sunxi-ng: Add A80 CCU 2017-01-30 08:37:30 +01:00
ccu-sun50i-a64.c clk: sunxi-ng: a64: Allow parent change for VE clock 2018-12-10 11:19:26 -08:00
ccu-sun50i-a64.h dt-bindings: clock: sun50i-a64-ccu: Add PLL_VIDEO0 macro 2018-09-05 09:19:59 +02:00
ccu-sun50i-h6-r.c clk: sunxi-ng: add support for H6 PRCM CCU 2018-05-04 17:05:46 +02:00
ccu-sun50i-h6-r.h clk: sunxi-ng: add support for H6 PRCM CCU 2018-05-04 17:05:46 +02:00
ccu-sun50i-h6.c clk: sunxi-ng: h6: Set video PLLs limits 2018-11-05 10:21:43 +01:00
ccu-sun50i-h6.h clk: sunxi-ng: add missing hdmi-slow clock for H6 CCU 2018-03-21 12:27:13 +01:00
ccu-suniv-f1c100s.c clk: sunxi-ng: add support for suniv F1C100s SoC 2018-12-04 08:41:13 +01:00
ccu-suniv-f1c100s.h clk: sunxi-ng: add support for suniv F1C100s SoC 2018-12-04 08:41:13 +01:00
Kconfig clk: sunxi-ng: add support for suniv F1C100s SoC 2018-12-04 08:41:13 +01:00
Makefile clk: sunxi-ng: add support for suniv F1C100s SoC 2018-12-04 08:41:13 +01:00