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23a5fba4d9
Some PCI host controllers do not expose a configuration space for the root port PCI bridge. Due to this, the Marvell Armada 370/38x/XP PCI controller driver (pci-mvebu) emulates a root port PCI bridge configuration space, and uses that to (among other things) dynamically create the memory windows that correspond to the PCI MEM and I/O regions. Since we now need to add a very similar logic for the Marvell Armada 37xx PCI controller driver (pci-aardvark), instead of duplicating the code, we create in this commit a common logic called pci-bridge-emul. The idea of this logic is to emulate a root port PCI bridge configuration space by providing configuration space read/write operations, and faking behind the scenes the configuration space of a PCI bridge. A PCI host controller driver simply has to call pci_bridge_emul_conf_read() and pci_bridge_emul_conf_write() to read/write the configuration space of the bridge. By default, the PCI bridge configuration space is simply emulated by a chunk of memory, but the PCI host controller can override the behavior of the read and write operations on a per-register basis to do additional actions if needed. We take care of complying with the behavior of the PCI configuration space registers in terms of bits that are read-write, read-only, reserved and write-1-to-clear. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Russell King <rmk+kernel@armlinux.org.uk>
125 lines
2.9 KiB
C
125 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __PCI_BRIDGE_EMUL_H__
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#define __PCI_BRIDGE_EMUL_H__
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#include <linux/kernel.h>
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/* PCI configuration space of a PCI-to-PCI bridge. */
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struct pci_bridge_emul_conf {
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u16 vendor;
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u16 device;
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u16 command;
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u16 status;
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u32 class_revision;
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u8 cache_line_size;
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u8 latency_timer;
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u8 header_type;
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u8 bist;
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u32 bar[2];
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u8 primary_bus;
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u8 secondary_bus;
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u8 subordinate_bus;
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u8 secondary_latency_timer;
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u8 iobase;
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u8 iolimit;
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u16 secondary_status;
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u16 membase;
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u16 memlimit;
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u16 pref_mem_base;
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u16 pref_mem_limit;
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u32 prefbaseupper;
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u32 preflimitupper;
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u16 iobaseupper;
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u16 iolimitupper;
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u8 capabilities_pointer;
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u8 reserve[3];
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u32 romaddr;
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u8 intline;
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u8 intpin;
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u16 bridgectrl;
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};
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/* PCI configuration space of the PCIe capabilities */
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struct pci_bridge_emul_pcie_conf {
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u8 cap_id;
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u8 next;
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u16 cap;
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u32 devcap;
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u16 devctl;
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u16 devsta;
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u32 lnkcap;
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u16 lnkctl;
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u16 lnksta;
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u32 slotcap;
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u16 slotctl;
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u16 slotsta;
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u16 rootctl;
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u16 rsvd;
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u32 rootsta;
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u32 devcap2;
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u16 devctl2;
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u16 devsta2;
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u32 lnkcap2;
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u16 lnkctl2;
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u16 lnksta2;
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u32 slotcap2;
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u16 slotctl2;
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u16 slotsta2;
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};
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struct pci_bridge_emul;
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typedef enum { PCI_BRIDGE_EMUL_HANDLED,
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PCI_BRIDGE_EMUL_NOT_HANDLED } pci_bridge_emul_read_status_t;
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struct pci_bridge_emul_ops {
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/*
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* Called when reading from the regular PCI bridge
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* configuration space. Return PCI_BRIDGE_EMUL_HANDLED when the
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* operation has handled the read operation and filled in the
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* *value, or PCI_BRIDGE_EMUL_NOT_HANDLED when the read should
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* be emulated by the common code by reading from the
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* in-memory copy of the configuration space.
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*/
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pci_bridge_emul_read_status_t (*read_base)(struct pci_bridge_emul *bridge,
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int reg, u32 *value);
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/*
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* Same as ->read_base(), except it is for reading from the
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* PCIe capability configuration space.
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*/
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pci_bridge_emul_read_status_t (*read_pcie)(struct pci_bridge_emul *bridge,
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int reg, u32 *value);
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/*
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* Called when writing to the regular PCI bridge configuration
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* space. old is the current value, new is the new value being
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* written, and mask indicates which parts of the value are
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* being changed.
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*/
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void (*write_base)(struct pci_bridge_emul *bridge, int reg,
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u32 old, u32 new, u32 mask);
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/*
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* Same as ->write_base(), except it is for writing from the
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* PCIe capability configuration space.
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*/
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void (*write_pcie)(struct pci_bridge_emul *bridge, int reg,
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u32 old, u32 new, u32 mask);
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};
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struct pci_bridge_emul {
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struct pci_bridge_emul_conf conf;
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struct pci_bridge_emul_pcie_conf pcie_conf;
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struct pci_bridge_emul_ops *ops;
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void *data;
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bool has_pcie;
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};
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void pci_bridge_emul_init(struct pci_bridge_emul *bridge);
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int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where,
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int size, u32 *value);
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int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,
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int size, u32 value);
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#endif /* __PCI_BRIDGE_EMUL_H__ */
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