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https://github.com/edk2-porting/linux-next.git
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cbe7fc8aae
One register may have several fields to control some clocks. It is possible that the read/write values of some fields may map to different real functional values, so writing to the other fields in the same register may break a working clock tree. A real case is the aclk_podf field in the register 'CCM Serial Clock Multiplexer Register 1' of i.MX6Q/SDL SoC. This patch introduces a fixup hook for divider clock which is called before writing a value to clock registers to support this kind of divider clocks. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
130 lines
3.3 KiB
C
130 lines
3.3 KiB
C
/*
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* Copyright (C) 2013 Freescale Semiconductor, Inc.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include "clk.h"
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#define to_clk_div(_hw) container_of(_hw, struct clk_divider, hw)
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#define div_mask(d) ((1 << (d->width)) - 1)
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/**
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* struct clk_fixup_div - imx integer fixup divider clock
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* @divider: the parent class
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* @ops: pointer to clk_ops of parent class
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* @fixup: a hook to fixup the write value
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*
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* The imx fixup divider clock is a subclass of basic clk_divider
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* with an addtional fixup hook.
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*/
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struct clk_fixup_div {
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struct clk_divider divider;
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const struct clk_ops *ops;
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void (*fixup)(u32 *val);
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};
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static inline struct clk_fixup_div *to_clk_fixup_div(struct clk_hw *hw)
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{
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struct clk_divider *divider = to_clk_div(hw);
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return container_of(divider, struct clk_fixup_div, divider);
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}
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static unsigned long clk_fixup_div_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_fixup_div *fixup_div = to_clk_fixup_div(hw);
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return fixup_div->ops->recalc_rate(&fixup_div->divider.hw, parent_rate);
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}
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static long clk_fixup_div_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct clk_fixup_div *fixup_div = to_clk_fixup_div(hw);
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return fixup_div->ops->round_rate(&fixup_div->divider.hw, rate, prate);
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}
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static int clk_fixup_div_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_fixup_div *fixup_div = to_clk_fixup_div(hw);
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struct clk_divider *div = to_clk_div(hw);
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unsigned int divider, value;
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unsigned long flags = 0;
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u32 val;
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divider = parent_rate / rate;
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/* Zero based divider */
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value = divider - 1;
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if (value > div_mask(div))
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value = div_mask(div);
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spin_lock_irqsave(div->lock, flags);
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val = readl(div->reg);
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val &= ~(div_mask(div) << div->shift);
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val |= value << div->shift;
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fixup_div->fixup(&val);
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writel(val, div->reg);
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spin_unlock_irqrestore(div->lock, flags);
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return 0;
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}
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static const struct clk_ops clk_fixup_div_ops = {
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.recalc_rate = clk_fixup_div_recalc_rate,
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.round_rate = clk_fixup_div_round_rate,
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.set_rate = clk_fixup_div_set_rate,
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};
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struct clk *imx_clk_fixup_divider(const char *name, const char *parent,
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void __iomem *reg, u8 shift, u8 width,
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void (*fixup)(u32 *val))
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{
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struct clk_fixup_div *fixup_div;
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struct clk *clk;
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struct clk_init_data init;
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if (!fixup)
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return ERR_PTR(-EINVAL);
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fixup_div = kzalloc(sizeof(*fixup_div), GFP_KERNEL);
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if (!fixup_div)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &clk_fixup_div_ops;
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init.flags = CLK_SET_RATE_PARENT;
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init.parent_names = parent ? &parent : NULL;
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init.num_parents = parent ? 1 : 0;
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fixup_div->divider.reg = reg;
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fixup_div->divider.shift = shift;
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fixup_div->divider.width = width;
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fixup_div->divider.lock = &imx_ccm_lock;
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fixup_div->divider.hw.init = &init;
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fixup_div->ops = &clk_divider_ops;
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fixup_div->fixup = fixup;
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clk = clk_register(NULL, &fixup_div->divider.hw);
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if (IS_ERR(clk))
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kfree(fixup_div);
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return clk;
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}
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