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278407a53c
The previous version of the dwc2 overlay set the RX FIFO size to 256 4-byte words. This is not enough for 1024 bytes of the largest isochronous high speed packet allowed, because it doesn't take into account extra space needed by dwc2. RX FIFO's size is calculated based on the following (in 4byte words): - 13 locations for SETUP packets 5*n + 8 for Slave and Buffer DMA mode where n is number of control endpoints which is 1 on the bcm283x core - 1 location for Global OUT NAK - 2 * 257 locations for status information and the received packet. Typically two spaces are recommended so that when the previous packet is being transferred to AHB, the USB can receive the subsequent packet. - 10 * 1 location for transfer complete status for last packet of each endpoint. The bcm283x core has 5 IN and 5 OUT EPs - 10 * 1 additional location for EPDisable status for each endpoint - 5 * 2 additional locations are recommended for each OUT endpoint Total is 558 locations. Signed-off-by: Phil Elwell <phil@raspberrypi.com> Signed-off-by: Pavel Hofman <pavel.hofman@ivitera.com> Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Link: https://lore.kernel.org/r/e9e7d070-593c-122f-3a5c-2435bb147ab2@ivitera.com/
8 lines
172 B
Plaintext
8 lines
172 B
Plaintext
// SPDX-License-Identifier: GPL-2.0
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&usb {
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dr_mode = "peripheral";
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g-rx-fifo-size = <558>;
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g-np-tx-fifo-size = <32>;
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g-tx-fifo-size = <256 256 512 512 512 768 768>;
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};
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