mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-25 21:54:06 +08:00
291852e879
twl-core driver and to fix omap1_defconfig compile when led driver changes and omap sparse IRQ changes are merged together. Also fix warnings for omaps not using pinctrl framework yet. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJQV9rrAAoJEBvUPslcq6Vz2AEQAIwbb/tKUgxubP6i31fuy/33 rP5RsgEMcnh3lD81+3G3hWECvxkfbs2LM06qi20YG90SPXYVd9koIWil407gvcTQ Nqq+36QBDsQo06ou1Pmy0DeBJ8yo2j3YU+lB6m+Qn7WS+KPqrebt/DMFdMW3Yfc3 zZ87DMfw/5S787z2Uru2CLGLpgv3bOooLvJYv0xBgkKTsRmJGIKJQJ7QoXIQMves 0sLAm/nORu7UU7WvYHd+tU/gC4svfm3WEL+QX4vNvPszCQdTayh7kdZN02eaNLJF vTUNiKjsW/xmda8+XS6YhP6lPFTPoCkDJWrIZqSWFaCnIIpsQZ+IBNdQMiB8uLtR eMdngBqIDTmRo5BOLMM/6eU2yzZ/PLeJI1pMQOTylgz2qaugQEnd77mIzEj6sNVn qSNtAwXTiBEhvA+8cjgsePnJxNtBdwcZ1c8YpEWigFC3cGOl3vHpt0XimIUfrkYX kKMHnVe9WHQGPFXdkA48ZXrACwzrDb1/3GUVbtGM7rX6/OiS6b4iJzplvBN4j1t1 eOH670dVbU2LhkStHhzV2rbQm7LUyVECkn+CGh13VRJDQrVlzA70g6Vp2KBNkgM+ bxyE7sirHHtzeJtFelYGeuRJ1RULAPxPBrVX7kPsrwcSAshKFnuAC6f9IQjCy3jf uYcmix5Qg14mN18H0l6S =omEP -----END PGP SIGNATURE----- Merge tag 'cleanup-fixes-for-v3.7' into test_v3.6-rc6_ocb3.7_cff3.7_odaf3.7 These fixes are needed to fix non-omap build breakage for twl-core driver and to fix omap1_defconfig compile when led driver changes and omap sparse IRQ changes are merged together. Also fix warnings for omaps not using pinctrl framework yet.
102 lines
2.5 KiB
C
102 lines
2.5 KiB
C
/*
|
|
* OMAP3-specific clock framework functions
|
|
*
|
|
* Copyright (C) 2007-2008 Texas Instruments, Inc.
|
|
* Copyright (C) 2007-2010 Nokia Corporation
|
|
*
|
|
* Paul Walmsley
|
|
* Jouni Högander
|
|
*
|
|
* Parts of this code are based on code written by
|
|
* Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
#undef DEBUG
|
|
|
|
#include <linux/kernel.h>
|
|
#include <linux/errno.h>
|
|
#include <linux/clk.h>
|
|
#include <linux/io.h>
|
|
|
|
#include <plat/clock.h>
|
|
|
|
#include "soc.h"
|
|
#include "clock.h"
|
|
#include "clock3xxx.h"
|
|
#include "prm2xxx_3xxx.h"
|
|
#include "prm-regbits-34xx.h"
|
|
#include "cm2xxx_3xxx.h"
|
|
#include "cm-regbits-34xx.h"
|
|
|
|
/*
|
|
* DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
|
|
* that are sourced by DPLL5, and both of these require this clock
|
|
* to be at 120 MHz for proper operation.
|
|
*/
|
|
#define DPLL5_FREQ_FOR_USBHOST 120000000
|
|
|
|
/* needed by omap3_core_dpll_m2_set_rate() */
|
|
struct clk *sdrc_ick_p, *arm_fck_p;
|
|
|
|
int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
|
|
{
|
|
/*
|
|
* According to the 12-5 CDP code from TI, "Limitation 2.5"
|
|
* on 3430ES1 prevents us from changing DPLL multipliers or dividers
|
|
* on DPLL4.
|
|
*/
|
|
if (omap_rev() == OMAP3430_REV_ES1_0) {
|
|
pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
return omap3_noncore_dpll_set_rate(clk, rate);
|
|
}
|
|
|
|
void __init omap3_clk_lock_dpll5(void)
|
|
{
|
|
struct clk *dpll5_clk;
|
|
struct clk *dpll5_m2_clk;
|
|
|
|
dpll5_clk = clk_get(NULL, "dpll5_ck");
|
|
clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
|
|
clk_enable(dpll5_clk);
|
|
|
|
/* Program dpll5_m2_clk divider for no division */
|
|
dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
|
|
clk_enable(dpll5_m2_clk);
|
|
clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
|
|
|
|
clk_disable(dpll5_m2_clk);
|
|
clk_disable(dpll5_clk);
|
|
return;
|
|
}
|
|
|
|
/* Common clock code */
|
|
|
|
/*
|
|
* Switch the MPU rate if specified on cmdline. We cannot do this
|
|
* early until cmdline is parsed. XXX This should be removed from the
|
|
* clock code and handled by the OPP layer code in the near future.
|
|
*/
|
|
static int __init omap3xxx_clk_arch_init(void)
|
|
{
|
|
int ret;
|
|
|
|
if (!cpu_is_omap34xx())
|
|
return 0;
|
|
|
|
ret = omap2_clk_switch_mpurate_at_boot("dpll1_ck");
|
|
if (!ret)
|
|
omap2_clk_print_new_rates("osc_sys_ck", "core_ck", "arm_fck");
|
|
|
|
return ret;
|
|
}
|
|
|
|
arch_initcall(omap3xxx_clk_arch_init);
|
|
|
|
|