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a439fe51a1
The majority of this patch was created by the following script: *** ASM=arch/sparc/include/asm mkdir -p $ASM git mv include/asm-sparc64/ftrace.h $ASM git rm include/asm-sparc64/* git mv include/asm-sparc/* $ASM sed -ie 's/asm-sparc64/asm/g' $ASM/* sed -ie 's/asm-sparc/asm/g' $ASM/* *** The rest was an update of the top-level Makefile to use sparc for header files when sparc64 is being build. And a small fixlet to pick up the correct unistd.h from sparc64 code. Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
155 lines
4.7 KiB
C
155 lines
4.7 KiB
C
#ifndef _ASM_SPARC64_DMA_MAPPING_H
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#define _ASM_SPARC64_DMA_MAPPING_H
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#include <linux/scatterlist.h>
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#include <linux/mm.h>
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#define DMA_ERROR_CODE (~(dma_addr_t)0x0)
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struct dma_ops {
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void *(*alloc_coherent)(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t flag);
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void (*free_coherent)(struct device *dev, size_t size,
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void *cpu_addr, dma_addr_t dma_handle);
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dma_addr_t (*map_single)(struct device *dev, void *cpu_addr,
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size_t size,
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enum dma_data_direction direction);
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void (*unmap_single)(struct device *dev, dma_addr_t dma_addr,
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size_t size,
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enum dma_data_direction direction);
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int (*map_sg)(struct device *dev, struct scatterlist *sg, int nents,
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enum dma_data_direction direction);
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void (*unmap_sg)(struct device *dev, struct scatterlist *sg,
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int nhwentries,
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enum dma_data_direction direction);
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void (*sync_single_for_cpu)(struct device *dev,
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dma_addr_t dma_handle, size_t size,
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enum dma_data_direction direction);
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void (*sync_sg_for_cpu)(struct device *dev, struct scatterlist *sg,
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int nelems,
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enum dma_data_direction direction);
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};
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extern const struct dma_ops *dma_ops;
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extern int dma_supported(struct device *dev, u64 mask);
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extern int dma_set_mask(struct device *dev, u64 dma_mask);
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static inline void *dma_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t flag)
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{
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return dma_ops->alloc_coherent(dev, size, dma_handle, flag);
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}
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static inline void dma_free_coherent(struct device *dev, size_t size,
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void *cpu_addr, dma_addr_t dma_handle)
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{
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dma_ops->free_coherent(dev, size, cpu_addr, dma_handle);
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}
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static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
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size_t size,
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enum dma_data_direction direction)
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{
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return dma_ops->map_single(dev, cpu_addr, size, direction);
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}
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static inline void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
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size_t size,
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enum dma_data_direction direction)
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{
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dma_ops->unmap_single(dev, dma_addr, size, direction);
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}
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static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t size,
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enum dma_data_direction direction)
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{
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return dma_ops->map_single(dev, page_address(page) + offset,
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size, direction);
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}
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static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
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size_t size,
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enum dma_data_direction direction)
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{
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dma_ops->unmap_single(dev, dma_address, size, direction);
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}
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static inline int dma_map_sg(struct device *dev, struct scatterlist *sg,
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int nents, enum dma_data_direction direction)
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{
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return dma_ops->map_sg(dev, sg, nents, direction);
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}
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static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
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int nents, enum dma_data_direction direction)
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{
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dma_ops->unmap_sg(dev, sg, nents, direction);
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}
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static inline void dma_sync_single_for_cpu(struct device *dev,
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dma_addr_t dma_handle, size_t size,
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enum dma_data_direction direction)
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{
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dma_ops->sync_single_for_cpu(dev, dma_handle, size, direction);
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}
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static inline void dma_sync_single_for_device(struct device *dev,
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dma_addr_t dma_handle,
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size_t size,
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enum dma_data_direction direction)
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{
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/* No flushing needed to sync cpu writes to the device. */
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}
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static inline void dma_sync_single_range_for_cpu(struct device *dev,
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dma_addr_t dma_handle,
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unsigned long offset,
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size_t size,
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enum dma_data_direction direction)
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{
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dma_sync_single_for_cpu(dev, dma_handle+offset, size, direction);
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}
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static inline void dma_sync_single_range_for_device(struct device *dev,
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dma_addr_t dma_handle,
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unsigned long offset,
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size_t size,
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enum dma_data_direction direction)
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{
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/* No flushing needed to sync cpu writes to the device. */
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}
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static inline void dma_sync_sg_for_cpu(struct device *dev,
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struct scatterlist *sg, int nelems,
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enum dma_data_direction direction)
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{
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dma_ops->sync_sg_for_cpu(dev, sg, nelems, direction);
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}
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static inline void dma_sync_sg_for_device(struct device *dev,
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struct scatterlist *sg, int nelems,
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enum dma_data_direction direction)
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{
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/* No flushing needed to sync cpu writes to the device. */
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}
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static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
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{
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return (dma_addr == DMA_ERROR_CODE);
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}
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static inline int dma_get_cache_alignment(void)
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{
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/* no easy way to get cache size on all processors, so return
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* the maximum possible, to be safe */
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return (1 << INTERNODE_CACHE_SHIFT);
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}
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#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
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#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
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#define dma_is_consistent(d, h) (1)
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#endif /* _ASM_SPARC64_DMA_MAPPING_H */
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