mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-21 11:44:01 +08:00
94bd32792e
Current ARM7 Cirrus Logic product line contains only 3 cpu. EP7312 - Fully functional. EP7309 - Missing SDRAM interface. EP7311 - Missing DAI. It makes no sense to separate the header files to identify these differences, it is only necessary to keep in mind the presence or lack of any features of a specific CPU when writing code. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
65 lines
1.6 KiB
Plaintext
65 lines
1.6 KiB
Plaintext
if ARCH_CLPS711X
|
|
|
|
menu "CLPS711X/EP721X/EP731X Implementations"
|
|
|
|
config ARCH_AUTCPU12
|
|
bool "AUTCPU12"
|
|
help
|
|
Say Y if you intend to run the kernel on the autronix autcpu12
|
|
board. This board is based on a Cirrus Logic CS89712.
|
|
|
|
config ARCH_CDB89712
|
|
bool "CDB89712"
|
|
select ISA
|
|
help
|
|
This is an evaluation board from Cirrus for the CS89712 processor.
|
|
The board includes 2 serial ports, Ethernet, IRDA, and expansion
|
|
headers. It comes with 16 MB SDRAM and 8 MB flash ROM.
|
|
|
|
config ARCH_CEIVA
|
|
bool "CEIVA"
|
|
help
|
|
Say Y here if you intend to run this kernel on the Ceiva/Polaroid
|
|
PhotoMax Digital Picture Frame.
|
|
|
|
config ARCH_CLEP7312
|
|
bool "CLEP7312"
|
|
help
|
|
Boards based on the Cirrus Logic 7212/7312 chips.
|
|
|
|
config ARCH_EDB7211
|
|
bool "EDB7211"
|
|
select ISA
|
|
select ARCH_SPARSEMEM_ENABLE
|
|
select ARCH_SELECT_MEMORY_MODEL
|
|
help
|
|
Say Y here if you intend to run this kernel on a Cirrus Logic EDB-7211
|
|
evaluation board.
|
|
|
|
config ARCH_P720T
|
|
bool "P720T"
|
|
help
|
|
Say Y here if you intend to run this kernel on the ARM Prospector
|
|
720T.
|
|
|
|
config ARCH_FORTUNET
|
|
bool "FORTUNET"
|
|
|
|
config EP72XX_ROM_BOOT
|
|
bool "EP721x/EP731x ROM boot"
|
|
help
|
|
If you say Y here, your CLPS711x-based kernel will use the bootstrap
|
|
mode memory map instead of the normal memory map.
|
|
|
|
Processors derived from the Cirrus CLPS711X core support two boot
|
|
modes. Normal mode boots from the external memory device at CS0.
|
|
Bootstrap mode rearranges parts of the memory map, placing an
|
|
internal 128 byte bootstrap ROM at CS0. This option performs the
|
|
address map changes required to support booting in this mode.
|
|
|
|
You almost surely want to say N here.
|
|
|
|
endmenu
|
|
|
|
endif
|