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UV supports really big systems. So big, in fact, that the APICID register does not contain enough bits to contain an APICID that is unique across all cpus. The UV BIOS supports 3 APICID modes: - legacy mode. This mode uses the old APIC mode where APICID is in bits [31:24] of the APICID register. - x2apic mode. This mode is whitebox-compatible. APICIDs are unique across all cpus. Standard x2apic APIC operations (Intel-defined) can be used for IPIs. The node identifier fits within the Intel-defined portion of the APICID register. - x2apic-uv mode. In this mode, the APICIDs on each node have unique IDs, but IDs on different node are not unique. For example, if each mode has 32 cpus, the APICIDs on each node might be 0 - 31. Every node has the same set of IDs. The UV hub is used to route IPIs/interrupts to the correct node. Traditional APIC operations WILL NOT WORK. In x2apic-uv mode, the ACPI tables all contain a full unique ID (note: exact bit layout still changing but the following is close): nnnnnnnnnnlc0cch n = unique node number l = socket number on board c = core h = hyperthread Only the "lc0cch" bits are written to the APICID register. The remaining bits are supplied by having the get_apic_id() function "OR" the extra bits into the value read from the APICID register. (Hmmm.. why not keep the ENTIRE APICID register in per-cpu data....) The x2apic-uv mode is recognized by the MADT table containing: oem_id = "SGI" oem_table_id = "UV-X" Signed-off-by: Jack Steiner <steiner@sgi.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
48 lines
1.3 KiB
C
48 lines
1.3 KiB
C
#ifndef _ASM_GENAPIC_H
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#define _ASM_GENAPIC_H 1
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/*
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* Copyright 2004 James Cleverdon, IBM.
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* Subject to the GNU Public License, v.2
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*
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* Generic APIC sub-arch data struct.
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*
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* Hacked for x86-64 by James Cleverdon from i386 architecture code by
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* Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
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* James Cleverdon.
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*/
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struct genapic {
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char *name;
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u32 int_delivery_mode;
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u32 int_dest_mode;
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int (*apic_id_registered)(void);
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cpumask_t (*target_cpus)(void);
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cpumask_t (*vector_allocation_domain)(int cpu);
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void (*init_apic_ldr)(void);
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/* ipi */
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void (*send_IPI_mask)(cpumask_t mask, int vector);
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void (*send_IPI_allbutself)(int vector);
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void (*send_IPI_all)(int vector);
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/* */
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unsigned int (*cpu_mask_to_apicid)(cpumask_t cpumask);
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unsigned int (*phys_pkg_id)(int index_msb);
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};
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extern struct genapic *genapic;
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extern struct genapic apic_flat;
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extern struct genapic apic_physflat;
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extern int acpi_madt_oem_check(char *, char *);
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enum uv_system_type {UV_NONE, UV_LEGACY_APIC, UV_X2APIC, UV_NON_UNIQUE_APIC};
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extern enum uv_system_type get_uv_system_type(void);
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extern int is_uv_system(void);
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extern struct genapic apic_x2apic_uv_x;
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DECLARE_PER_CPU(int, x2apic_extra_bits);
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extern void uv_cpu_init(void);
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extern int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip);
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#endif
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