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https://github.com/edk2-porting/linux-next.git
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ebd00c08e2
The clock generation system in the ep93xx uses two external oscillator's and two internal PLLs to derive all the internal clocks. Many of these internal clocks can be stopped to save power. This introduces a "parent" hierarchy for the clocks so that the users count can be correctly tracked for power management. The "parent" for the video clock can either be one of the PLL outputs or the external oscillator. In order to correctly track the "parent" for the video clock calc_clk_div() needed to be modified. It now returns an error code if the desired rate cannot be generated. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Acked-by: Ryan Mallon <ryan@bluewatersys.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
482 lines
12 KiB
C
482 lines
12 KiB
C
/*
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* arch/arm/mach-ep93xx/clock.c
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* Clock control for Cirrus EP93xx chips.
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*
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* Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or (at
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* your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/string.h>
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#include <linux/io.h>
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#include <linux/spinlock.h>
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#include <mach/hardware.h>
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#include <asm/clkdev.h>
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#include <asm/div64.h>
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struct clk {
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struct clk *parent;
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unsigned long rate;
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int users;
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int sw_locked;
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void __iomem *enable_reg;
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u32 enable_mask;
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unsigned long (*get_rate)(struct clk *clk);
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int (*set_rate)(struct clk *clk, unsigned long rate);
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};
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static unsigned long get_uart_rate(struct clk *clk);
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static int set_keytchclk_rate(struct clk *clk, unsigned long rate);
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static int set_div_rate(struct clk *clk, unsigned long rate);
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static struct clk clk_xtali = {
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.rate = EP93XX_EXT_CLK_RATE,
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};
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static struct clk clk_uart1 = {
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.parent = &clk_xtali,
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.sw_locked = 1,
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.enable_reg = EP93XX_SYSCON_DEVCFG,
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.enable_mask = EP93XX_SYSCON_DEVCFG_U1EN,
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.get_rate = get_uart_rate,
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};
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static struct clk clk_uart2 = {
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.parent = &clk_xtali,
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.sw_locked = 1,
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.enable_reg = EP93XX_SYSCON_DEVCFG,
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.enable_mask = EP93XX_SYSCON_DEVCFG_U2EN,
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.get_rate = get_uart_rate,
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};
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static struct clk clk_uart3 = {
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.parent = &clk_xtali,
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.sw_locked = 1,
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.enable_reg = EP93XX_SYSCON_DEVCFG,
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.enable_mask = EP93XX_SYSCON_DEVCFG_U3EN,
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.get_rate = get_uart_rate,
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};
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static struct clk clk_pll1 = {
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.parent = &clk_xtali,
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};
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static struct clk clk_f = {
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.parent = &clk_pll1,
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};
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static struct clk clk_h = {
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.parent = &clk_pll1,
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};
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static struct clk clk_p = {
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.parent = &clk_pll1,
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};
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static struct clk clk_pll2 = {
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.parent = &clk_xtali,
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};
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static struct clk clk_usb_host = {
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.parent = &clk_pll2,
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.enable_reg = EP93XX_SYSCON_PWRCNT,
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.enable_mask = EP93XX_SYSCON_PWRCNT_USH_EN,
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};
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static struct clk clk_keypad = {
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.parent = &clk_xtali,
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.sw_locked = 1,
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.enable_reg = EP93XX_SYSCON_KEYTCHCLKDIV,
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.enable_mask = EP93XX_SYSCON_KEYTCHCLKDIV_KEN,
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.set_rate = set_keytchclk_rate,
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};
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static struct clk clk_pwm = {
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.parent = &clk_xtali,
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.rate = EP93XX_EXT_CLK_RATE,
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};
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static struct clk clk_video = {
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.sw_locked = 1,
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.enable_reg = EP93XX_SYSCON_VIDCLKDIV,
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.enable_mask = EP93XX_SYSCON_CLKDIV_ENABLE,
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.set_rate = set_div_rate,
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};
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/* DMA Clocks */
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static struct clk clk_m2p0 = {
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.parent = &clk_h,
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.enable_reg = EP93XX_SYSCON_PWRCNT,
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.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P0,
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};
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static struct clk clk_m2p1 = {
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.parent = &clk_h,
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.enable_reg = EP93XX_SYSCON_PWRCNT,
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.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P1,
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};
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static struct clk clk_m2p2 = {
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.parent = &clk_h,
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.enable_reg = EP93XX_SYSCON_PWRCNT,
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.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P2,
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};
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static struct clk clk_m2p3 = {
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.parent = &clk_h,
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.enable_reg = EP93XX_SYSCON_PWRCNT,
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.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P3,
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};
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static struct clk clk_m2p4 = {
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.parent = &clk_h,
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.enable_reg = EP93XX_SYSCON_PWRCNT,
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.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P4,
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};
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static struct clk clk_m2p5 = {
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.parent = &clk_h,
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.enable_reg = EP93XX_SYSCON_PWRCNT,
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.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P5,
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};
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static struct clk clk_m2p6 = {
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.parent = &clk_h,
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.enable_reg = EP93XX_SYSCON_PWRCNT,
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.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P6,
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};
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static struct clk clk_m2p7 = {
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.parent = &clk_h,
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.enable_reg = EP93XX_SYSCON_PWRCNT,
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.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P7,
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};
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static struct clk clk_m2p8 = {
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.parent = &clk_h,
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.enable_reg = EP93XX_SYSCON_PWRCNT,
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.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P8,
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};
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static struct clk clk_m2p9 = {
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.parent = &clk_h,
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.enable_reg = EP93XX_SYSCON_PWRCNT,
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.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P9,
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};
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static struct clk clk_m2m0 = {
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.parent = &clk_h,
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.enable_reg = EP93XX_SYSCON_PWRCNT,
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.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M0,
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};
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static struct clk clk_m2m1 = {
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.parent = &clk_h,
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.enable_reg = EP93XX_SYSCON_PWRCNT,
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.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M1,
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};
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#define INIT_CK(dev,con,ck) \
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{ .dev_id = dev, .con_id = con, .clk = ck }
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static struct clk_lookup clocks[] = {
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INIT_CK(NULL, "xtali", &clk_xtali),
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INIT_CK("apb:uart1", NULL, &clk_uart1),
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INIT_CK("apb:uart2", NULL, &clk_uart2),
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INIT_CK("apb:uart3", NULL, &clk_uart3),
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INIT_CK(NULL, "pll1", &clk_pll1),
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INIT_CK(NULL, "fclk", &clk_f),
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INIT_CK(NULL, "hclk", &clk_h),
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INIT_CK(NULL, "pclk", &clk_p),
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INIT_CK(NULL, "pll2", &clk_pll2),
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INIT_CK("ep93xx-ohci", NULL, &clk_usb_host),
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INIT_CK("ep93xx-keypad", NULL, &clk_keypad),
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INIT_CK("ep93xx-fb", NULL, &clk_video),
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INIT_CK(NULL, "pwm_clk", &clk_pwm),
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INIT_CK(NULL, "m2p0", &clk_m2p0),
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INIT_CK(NULL, "m2p1", &clk_m2p1),
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INIT_CK(NULL, "m2p2", &clk_m2p2),
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INIT_CK(NULL, "m2p3", &clk_m2p3),
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INIT_CK(NULL, "m2p4", &clk_m2p4),
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INIT_CK(NULL, "m2p5", &clk_m2p5),
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INIT_CK(NULL, "m2p6", &clk_m2p6),
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INIT_CK(NULL, "m2p7", &clk_m2p7),
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INIT_CK(NULL, "m2p8", &clk_m2p8),
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INIT_CK(NULL, "m2p9", &clk_m2p9),
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INIT_CK(NULL, "m2m0", &clk_m2m0),
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INIT_CK(NULL, "m2m1", &clk_m2m1),
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};
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static DEFINE_SPINLOCK(clk_lock);
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static void __clk_enable(struct clk *clk)
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{
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if (!clk->users++) {
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if (clk->parent)
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__clk_enable(clk->parent);
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if (clk->enable_reg) {
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u32 v;
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v = __raw_readl(clk->enable_reg);
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v |= clk->enable_mask;
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if (clk->sw_locked)
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ep93xx_syscon_swlocked_write(v, clk->enable_reg);
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else
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__raw_writel(v, clk->enable_reg);
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}
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}
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}
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int clk_enable(struct clk *clk)
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{
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unsigned long flags;
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if (!clk)
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return -EINVAL;
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spin_lock_irqsave(&clk_lock, flags);
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__clk_enable(clk);
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spin_unlock_irqrestore(&clk_lock, flags);
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return 0;
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}
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EXPORT_SYMBOL(clk_enable);
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static void __clk_disable(struct clk *clk)
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{
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if (!--clk->users) {
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if (clk->enable_reg) {
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u32 v;
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v = __raw_readl(clk->enable_reg);
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v &= ~clk->enable_mask;
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if (clk->sw_locked)
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ep93xx_syscon_swlocked_write(v, clk->enable_reg);
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else
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__raw_writel(v, clk->enable_reg);
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}
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if (clk->parent)
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__clk_disable(clk->parent);
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}
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}
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void clk_disable(struct clk *clk)
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{
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unsigned long flags;
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if (!clk)
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return;
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spin_lock_irqsave(&clk_lock, flags);
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__clk_disable(clk);
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spin_unlock_irqrestore(&clk_lock, flags);
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}
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EXPORT_SYMBOL(clk_disable);
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static unsigned long get_uart_rate(struct clk *clk)
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{
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unsigned long rate = clk_get_rate(clk->parent);
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u32 value;
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value = __raw_readl(EP93XX_SYSCON_PWRCNT);
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if (value & EP93XX_SYSCON_PWRCNT_UARTBAUD)
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return rate;
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else
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return rate / 2;
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}
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unsigned long clk_get_rate(struct clk *clk)
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{
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if (clk->get_rate)
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return clk->get_rate(clk);
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return clk->rate;
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}
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EXPORT_SYMBOL(clk_get_rate);
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static int set_keytchclk_rate(struct clk *clk, unsigned long rate)
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{
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u32 val;
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u32 div_bit;
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val = __raw_readl(clk->enable_reg);
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/*
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* The Key Matrix and ADC clocks are configured using the same
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* System Controller register. The clock used will be either
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* 1/4 or 1/16 the external clock rate depending on the
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* EP93XX_SYSCON_KEYTCHCLKDIV_KDIV/EP93XX_SYSCON_KEYTCHCLKDIV_ADIV
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* bit being set or cleared.
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*/
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div_bit = clk->enable_mask >> 15;
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if (rate == EP93XX_KEYTCHCLK_DIV4)
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val |= div_bit;
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else if (rate == EP93XX_KEYTCHCLK_DIV16)
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val &= ~div_bit;
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else
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return -EINVAL;
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ep93xx_syscon_swlocked_write(val, clk->enable_reg);
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clk->rate = rate;
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return 0;
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}
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static int calc_clk_div(struct clk *clk, unsigned long rate,
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int *psel, int *esel, int *pdiv, int *div)
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{
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struct clk *mclk;
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unsigned long max_rate, actual_rate, mclk_rate, rate_err = -1;
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int i, found = 0, __div = 0, __pdiv = 0;
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/* Don't exceed the maximum rate */
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max_rate = max(max(clk_pll1.rate / 4, clk_pll2.rate / 4),
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clk_xtali.rate / 4);
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rate = min(rate, max_rate);
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/*
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* Try the two pll's and the external clock
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* Because the valid predividers are 2, 2.5 and 3, we multiply
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* all the clocks by 2 to avoid floating point math.
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*
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* This is based on the algorithm in the ep93xx raster guide:
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* http://be-a-maverick.com/en/pubs/appNote/AN269REV1.pdf
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*
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*/
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for (i = 0; i < 3; i++) {
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if (i == 0)
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mclk = &clk_xtali;
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else if (i == 1)
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mclk = &clk_pll1;
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else
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mclk = &clk_pll2;
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mclk_rate = mclk->rate * 2;
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/* Try each predivider value */
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for (__pdiv = 4; __pdiv <= 6; __pdiv++) {
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__div = mclk_rate / (rate * __pdiv);
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if (__div < 2 || __div > 127)
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continue;
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actual_rate = mclk_rate / (__pdiv * __div);
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if (!found || abs(actual_rate - rate) < rate_err) {
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*pdiv = __pdiv - 3;
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*div = __div;
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*psel = (i == 2);
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*esel = (i != 0);
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clk->parent = mclk;
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clk->rate = actual_rate;
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rate_err = abs(actual_rate - rate);
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found = 1;
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}
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}
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}
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if (!found)
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return -EINVAL;
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return 0;
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}
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static int set_div_rate(struct clk *clk, unsigned long rate)
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{
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int err, psel = 0, esel = 0, pdiv = 0, div = 0;
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u32 val;
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err = calc_clk_div(clk, rate, &psel, &esel, &pdiv, &div);
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if (err)
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return err;
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/* Clear the esel, psel, pdiv and div bits */
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val = __raw_readl(clk->enable_reg);
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val &= ~0x7fff;
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/* Set the new esel, psel, pdiv and div bits for the new clock rate */
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val |= (esel ? EP93XX_SYSCON_CLKDIV_ESEL : 0) |
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(psel ? EP93XX_SYSCON_CLKDIV_PSEL : 0) |
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(pdiv << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | div;
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ep93xx_syscon_swlocked_write(val, clk->enable_reg);
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return 0;
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}
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int clk_set_rate(struct clk *clk, unsigned long rate)
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{
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if (clk->set_rate)
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return clk->set_rate(clk, rate);
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return -EINVAL;
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}
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EXPORT_SYMBOL(clk_set_rate);
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static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
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static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
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static char pclk_divisors[] = { 1, 2, 4, 8 };
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/*
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* PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS
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*/
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static unsigned long calc_pll_rate(u32 config_word)
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{
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unsigned long long rate;
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int i;
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rate = clk_xtali.rate;
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rate *= ((config_word >> 11) & 0x1f) + 1; /* X1FBD */
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rate *= ((config_word >> 5) & 0x3f) + 1; /* X2FBD */
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do_div(rate, (config_word & 0x1f) + 1); /* X2IPD */
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for (i = 0; i < ((config_word >> 16) & 3); i++) /* PS */
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rate >>= 1;
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return (unsigned long)rate;
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}
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static void __init ep93xx_dma_clock_init(void)
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{
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clk_m2p0.rate = clk_h.rate;
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clk_m2p1.rate = clk_h.rate;
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clk_m2p2.rate = clk_h.rate;
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clk_m2p3.rate = clk_h.rate;
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clk_m2p4.rate = clk_h.rate;
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clk_m2p5.rate = clk_h.rate;
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clk_m2p6.rate = clk_h.rate;
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clk_m2p7.rate = clk_h.rate;
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clk_m2p8.rate = clk_h.rate;
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clk_m2p9.rate = clk_h.rate;
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clk_m2m0.rate = clk_h.rate;
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clk_m2m1.rate = clk_h.rate;
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}
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static int __init ep93xx_clock_init(void)
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{
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u32 value;
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int i;
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value = __raw_readl(EP93XX_SYSCON_CLOCK_SET1);
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if (!(value & 0x00800000)) { /* PLL1 bypassed? */
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clk_pll1.rate = clk_xtali.rate;
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} else {
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clk_pll1.rate = calc_pll_rate(value);
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}
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clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7];
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clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7];
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clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3];
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ep93xx_dma_clock_init();
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value = __raw_readl(EP93XX_SYSCON_CLOCK_SET2);
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if (!(value & 0x00080000)) { /* PLL2 bypassed? */
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clk_pll2.rate = clk_xtali.rate;
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} else if (value & 0x00040000) { /* PLL2 enabled? */
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clk_pll2.rate = calc_pll_rate(value);
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} else {
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|
clk_pll2.rate = 0;
|
|
}
|
|
clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1);
|
|
|
|
printk(KERN_INFO "ep93xx: PLL1 running at %ld MHz, PLL2 at %ld MHz\n",
|
|
clk_pll1.rate / 1000000, clk_pll2.rate / 1000000);
|
|
printk(KERN_INFO "ep93xx: FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n",
|
|
clk_f.rate / 1000000, clk_h.rate / 1000000,
|
|
clk_p.rate / 1000000);
|
|
|
|
for (i = 0; i < ARRAY_SIZE(clocks); i++)
|
|
clkdev_add(&clocks[i]);
|
|
return 0;
|
|
}
|
|
arch_initcall(ep93xx_clock_init);
|