mirror of
https://github.com/edk2-porting/linux-next.git
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1de3377555
This will cause a subtle behaviour change on GPUs that are in mixed-memory configurations in that VRAM in the degraded section of VRAM will no longer be used for TTM buffer objects. That section of VRAM is not meant to be used for displayable/compressed surfaces, and we have no reliable way with the current interfaces to be able to make that decision properly. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
362 lines
9.3 KiB
C
362 lines
9.3 KiB
C
/*
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* Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA,
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* All Rights Reserved.
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* Copyright (c) 2009 VMware, Inc., Palo Alto, CA., USA,
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sub license,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "nouveau_drv.h"
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#include "nouveau_gem.h"
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#include "nouveau_mem.h"
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#include "nouveau_ttm.h"
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#include <drm/drm_legacy.h>
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#include <core/tegra.h>
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static int
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nouveau_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
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{
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return 0;
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}
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static int
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nouveau_manager_fini(struct ttm_mem_type_manager *man)
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{
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return 0;
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}
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static void
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nouveau_manager_del(struct ttm_mem_type_manager *man, struct ttm_mem_reg *reg)
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{
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nouveau_mem_del(reg);
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}
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static void
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nouveau_manager_debug(struct ttm_mem_type_manager *man,
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struct drm_printer *printer)
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{
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}
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static void
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nouveau_vram_manager_del(struct ttm_mem_type_manager *man,
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struct ttm_mem_reg *reg)
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{
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struct nvkm_memory *memory = nouveau_mem(reg)->_mem->memory;
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nouveau_mem_del(reg);
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nvkm_memory_unref(&memory);
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}
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static int
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nouveau_vram_manager_new(struct ttm_mem_type_manager *man,
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struct ttm_buffer_object *bo,
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const struct ttm_place *place,
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struct ttm_mem_reg *reg)
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{
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struct nouveau_bo *nvbo = nouveau_bo(bo);
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struct nouveau_drm *drm = nvbo->cli->drm;
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struct nouveau_mem *mem;
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int ret;
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if (drm->client.device.info.ram_size == 0)
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return -ENOMEM;
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ret = nouveau_mem_new(&drm->master, nvbo->kind, nvbo->comp, reg);
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mem = nouveau_mem(reg);
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if (ret)
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return ret;
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ret = nouveau_mem_vram(reg, nvbo->contig, nvbo->page);
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if (ret) {
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nouveau_mem_del(reg);
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if (ret == -ENOSPC) {
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reg->mm_node = NULL;
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return 0;
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}
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return ret;
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}
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return 0;
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}
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const struct ttm_mem_type_manager_func nouveau_vram_manager = {
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.init = nouveau_manager_init,
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.takedown = nouveau_manager_fini,
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.get_node = nouveau_vram_manager_new,
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.put_node = nouveau_vram_manager_del,
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.debug = nouveau_manager_debug,
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};
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static int
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nouveau_gart_manager_new(struct ttm_mem_type_manager *man,
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struct ttm_buffer_object *bo,
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const struct ttm_place *place,
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struct ttm_mem_reg *reg)
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{
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struct nouveau_bo *nvbo = nouveau_bo(bo);
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struct nouveau_drm *drm = nvbo->cli->drm;
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struct nouveau_mem *mem;
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int ret;
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ret = nouveau_mem_new(&drm->master, nvbo->kind, nvbo->comp, reg);
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mem = nouveau_mem(reg);
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if (ret)
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return ret;
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mem->_mem = &mem->__mem;
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reg->start = 0;
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return 0;
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}
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const struct ttm_mem_type_manager_func nouveau_gart_manager = {
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.init = nouveau_manager_init,
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.takedown = nouveau_manager_fini,
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.get_node = nouveau_gart_manager_new,
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.put_node = nouveau_manager_del,
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.debug = nouveau_manager_debug
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};
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static int
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nv04_gart_manager_new(struct ttm_mem_type_manager *man,
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struct ttm_buffer_object *bo,
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const struct ttm_place *place,
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struct ttm_mem_reg *reg)
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{
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struct nouveau_bo *nvbo = nouveau_bo(bo);
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struct nouveau_drm *drm = nvbo->cli->drm;
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struct nouveau_mem *mem;
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struct nvkm_mmu *mmu = nvxx_mmu(&drm->client.device);
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int ret;
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ret = nouveau_mem_new(&drm->master, nvbo->kind, nvbo->comp, reg);
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mem = nouveau_mem(reg);
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if (ret)
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return ret;
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ret = nvkm_vm_get(mmu->vmm, reg->num_pages << 12, 12,
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NV_MEM_ACCESS_RW, &mem->vma[0]);
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if (ret) {
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nouveau_mem_del(reg);
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if (ret == -ENOSPC) {
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reg->mm_node = NULL;
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return 0;
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}
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return ret;
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}
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mem->_mem = &mem->__mem;
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reg->start = mem->vma[0].addr >> PAGE_SHIFT;
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return 0;
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}
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const struct ttm_mem_type_manager_func nv04_gart_manager = {
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.init = nouveau_manager_init,
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.takedown = nouveau_manager_fini,
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.get_node = nv04_gart_manager_new,
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.put_node = nouveau_manager_del,
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.debug = nouveau_manager_debug
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};
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int
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nouveau_ttm_mmap(struct file *filp, struct vm_area_struct *vma)
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{
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struct drm_file *file_priv = filp->private_data;
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struct nouveau_drm *drm = nouveau_drm(file_priv->minor->dev);
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if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
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return drm_legacy_mmap(filp, vma);
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return ttm_bo_mmap(filp, vma, &drm->ttm.bdev);
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}
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static int
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nouveau_ttm_mem_global_init(struct drm_global_reference *ref)
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{
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return ttm_mem_global_init(ref->object);
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}
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static void
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nouveau_ttm_mem_global_release(struct drm_global_reference *ref)
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{
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ttm_mem_global_release(ref->object);
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}
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int
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nouveau_ttm_global_init(struct nouveau_drm *drm)
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{
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struct drm_global_reference *global_ref;
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int ret;
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global_ref = &drm->ttm.mem_global_ref;
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global_ref->global_type = DRM_GLOBAL_TTM_MEM;
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global_ref->size = sizeof(struct ttm_mem_global);
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global_ref->init = &nouveau_ttm_mem_global_init;
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global_ref->release = &nouveau_ttm_mem_global_release;
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ret = drm_global_item_ref(global_ref);
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if (unlikely(ret != 0)) {
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DRM_ERROR("Failed setting up TTM memory accounting\n");
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drm->ttm.mem_global_ref.release = NULL;
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return ret;
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}
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drm->ttm.bo_global_ref.mem_glob = global_ref->object;
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global_ref = &drm->ttm.bo_global_ref.ref;
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global_ref->global_type = DRM_GLOBAL_TTM_BO;
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global_ref->size = sizeof(struct ttm_bo_global);
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global_ref->init = &ttm_bo_global_init;
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global_ref->release = &ttm_bo_global_release;
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ret = drm_global_item_ref(global_ref);
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if (unlikely(ret != 0)) {
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DRM_ERROR("Failed setting up TTM BO subsystem\n");
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drm_global_item_unref(&drm->ttm.mem_global_ref);
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drm->ttm.mem_global_ref.release = NULL;
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return ret;
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}
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return 0;
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}
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void
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nouveau_ttm_global_release(struct nouveau_drm *drm)
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{
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if (drm->ttm.mem_global_ref.release == NULL)
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return;
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drm_global_item_unref(&drm->ttm.bo_global_ref.ref);
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drm_global_item_unref(&drm->ttm.mem_global_ref);
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drm->ttm.mem_global_ref.release = NULL;
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}
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int
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nouveau_ttm_init(struct nouveau_drm *drm)
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{
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struct nvkm_device *device = nvxx_device(&drm->client.device);
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struct nvkm_pci *pci = device->pci;
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struct drm_device *dev = drm->dev;
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u8 bits;
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int ret;
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if (pci && pci->agp.bridge) {
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drm->agp.bridge = pci->agp.bridge;
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drm->agp.base = pci->agp.base;
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drm->agp.size = pci->agp.size;
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drm->agp.cma = pci->agp.cma;
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}
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bits = nvxx_mmu(&drm->client.device)->dma_bits;
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if (nvxx_device(&drm->client.device)->func->pci) {
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if (drm->agp.bridge)
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bits = 32;
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} else if (device->func->tegra) {
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struct nvkm_device_tegra *tegra = device->func->tegra(device);
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/*
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* If the platform can use a IOMMU, then the addressable DMA
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* space is constrained by the IOMMU bit
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*/
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if (tegra->func->iommu_bit)
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bits = min(bits, tegra->func->iommu_bit);
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}
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ret = dma_set_mask(dev->dev, DMA_BIT_MASK(bits));
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if (ret && bits != 32) {
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bits = 32;
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ret = dma_set_mask(dev->dev, DMA_BIT_MASK(bits));
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}
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if (ret)
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return ret;
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ret = dma_set_coherent_mask(dev->dev, DMA_BIT_MASK(bits));
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if (ret)
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dma_set_coherent_mask(dev->dev, DMA_BIT_MASK(32));
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ret = nouveau_ttm_global_init(drm);
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if (ret)
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return ret;
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ret = ttm_bo_device_init(&drm->ttm.bdev,
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drm->ttm.bo_global_ref.ref.object,
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&nouveau_bo_driver,
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dev->anon_inode->i_mapping,
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DRM_FILE_PAGE_OFFSET,
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bits <= 32 ? true : false);
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if (ret) {
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NV_ERROR(drm, "error initialising bo driver, %d\n", ret);
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return ret;
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}
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/* VRAM init */
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drm->gem.vram_available = drm->client.device.info.ram_user;
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arch_io_reserve_memtype_wc(device->func->resource_addr(device, 1),
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device->func->resource_size(device, 1));
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ret = ttm_bo_init_mm(&drm->ttm.bdev, TTM_PL_VRAM,
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drm->gem.vram_available >> PAGE_SHIFT);
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if (ret) {
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NV_ERROR(drm, "VRAM mm init failed, %d\n", ret);
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return ret;
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}
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drm->ttm.mtrr = arch_phys_wc_add(device->func->resource_addr(device, 1),
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device->func->resource_size(device, 1));
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/* GART init */
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if (!drm->agp.bridge) {
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drm->gem.gart_available = nvxx_mmu(&drm->client.device)->limit;
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} else {
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drm->gem.gart_available = drm->agp.size;
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}
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ret = ttm_bo_init_mm(&drm->ttm.bdev, TTM_PL_TT,
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drm->gem.gart_available >> PAGE_SHIFT);
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if (ret) {
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NV_ERROR(drm, "GART mm init failed, %d\n", ret);
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return ret;
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}
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NV_INFO(drm, "VRAM: %d MiB\n", (u32)(drm->gem.vram_available >> 20));
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NV_INFO(drm, "GART: %d MiB\n", (u32)(drm->gem.gart_available >> 20));
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return 0;
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}
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void
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nouveau_ttm_fini(struct nouveau_drm *drm)
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{
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struct nvkm_device *device = nvxx_device(&drm->client.device);
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ttm_bo_clean_mm(&drm->ttm.bdev, TTM_PL_VRAM);
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ttm_bo_clean_mm(&drm->ttm.bdev, TTM_PL_TT);
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ttm_bo_device_release(&drm->ttm.bdev);
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nouveau_ttm_global_release(drm);
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arch_phys_wc_del(drm->ttm.mtrr);
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drm->ttm.mtrr = 0;
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arch_io_free_memtype_wc(device->func->resource_addr(device, 1),
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device->func->resource_size(device, 1));
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}
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