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c2537ed9fb
Add guest exception handling for MIPS SIMD Architecture (MSA) floating point exceptions and MSA disabled exceptions. MSA floating point exceptions from the guest need passing to the guest kernel, so for these a guest MSAFPE is emulated. MSA disabled exceptions are normally handled by passing a reserved instruction exception to the guest (because no guest MSA was supported), but the hypervisor can now handle them if the guest has MSA by passing an MSA disabled exception to the guest, or if the guest has MSA enabled by transparently restoring the guest MSA context and enabling MSA and the FPU. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Gleb Natapov <gleb@kernel.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org
85 lines
1.5 KiB
C
85 lines
1.5 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* KVM/MIPS: COP0 access histogram
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*
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* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
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* Authors: Sanjay Lal <sanjayl@kymasys.com>
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*/
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#include <linux/kvm_host.h>
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char *kvm_mips_exit_types_str[MAX_KVM_MIPS_EXIT_TYPES] = {
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"WAIT",
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"CACHE",
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"Signal",
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"Interrupt",
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"COP0/1 Unusable",
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"TLB Mod",
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"TLB Miss (LD)",
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"TLB Miss (ST)",
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"Address Err (ST)",
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"Address Error (LD)",
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"System Call",
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"Reserved Inst",
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"Break Inst",
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"Trap Inst",
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"MSA FPE",
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"FPE",
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"MSA Disabled",
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"D-Cache Flushes",
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};
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char *kvm_cop0_str[N_MIPS_COPROC_REGS] = {
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"Index",
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"Random",
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"EntryLo0",
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"EntryLo1",
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"Context",
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"PG Mask",
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"Wired",
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"HWREna",
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"BadVAddr",
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"Count",
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"EntryHI",
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"Compare",
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"Status",
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"Cause",
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"EXC PC",
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"PRID",
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"Config",
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"LLAddr",
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"Watch Lo",
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"Watch Hi",
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"X Context",
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"Reserved",
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"Impl Dep",
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"Debug",
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"DEPC",
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"PerfCnt",
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"ErrCtl",
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"CacheErr",
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"TagLo",
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"TagHi",
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"ErrorEPC",
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"DESAVE"
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};
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void kvm_mips_dump_stats(struct kvm_vcpu *vcpu)
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{
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#ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
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int i, j;
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kvm_info("\nKVM VCPU[%d] COP0 Access Profile:\n", vcpu->vcpu_id);
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for (i = 0; i < N_MIPS_COPROC_REGS; i++) {
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for (j = 0; j < N_MIPS_COPROC_SEL; j++) {
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if (vcpu->arch.cop0->stat[i][j])
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kvm_info("%s[%d]: %lu\n", kvm_cop0_str[i], j,
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vcpu->arch.cop0->stat[i][j]);
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}
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}
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#endif
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}
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