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4e88a86213
Add a CPU_I6400 case to various switch statements, doing the same thing as for CPU_P5600. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10635/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
224 lines
4.6 KiB
C
224 lines
4.6 KiB
C
/*
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* MIPS SPRAM support
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* Copyright (C) 2007, 2008 MIPS Technologies, Inc.
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*/
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#include <linux/kernel.h>
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#include <linux/ptrace.h>
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#include <linux/stddef.h>
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#include <asm/fpu.h>
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#include <asm/mipsregs.h>
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#include <asm/r4kcache.h>
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#include <asm/hazards.h>
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/*
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* These definitions are correct for the 24K/34K/74K SPRAM sample
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* implementation. The 4KS interpreted the tags differently...
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*/
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#define SPRAM_TAG0_ENABLE 0x00000080
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#define SPRAM_TAG0_PA_MASK 0xfffff000
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#define SPRAM_TAG1_SIZE_MASK 0xfffff000
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#define SPRAM_TAG_STRIDE 8
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#define ERRCTL_SPRAM (1 << 28)
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/* errctl access */
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#define read_c0_errctl(x) read_c0_ecc(x)
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#define write_c0_errctl(x) write_c0_ecc(x)
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/*
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* Different semantics to the set_c0_* function built by __BUILD_SET_C0
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*/
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static unsigned int bis_c0_errctl(unsigned int set)
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{
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unsigned int res;
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res = read_c0_errctl();
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write_c0_errctl(res | set);
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return res;
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}
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static void ispram_store_tag(unsigned int offset, unsigned int data)
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{
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unsigned int errctl;
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/* enable SPRAM tag access */
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errctl = bis_c0_errctl(ERRCTL_SPRAM);
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ehb();
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write_c0_taglo(data);
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ehb();
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cache_op(Index_Store_Tag_I, CKSEG0|offset);
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ehb();
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write_c0_errctl(errctl);
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ehb();
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}
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static unsigned int ispram_load_tag(unsigned int offset)
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{
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unsigned int data;
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unsigned int errctl;
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/* enable SPRAM tag access */
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errctl = bis_c0_errctl(ERRCTL_SPRAM);
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ehb();
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cache_op(Index_Load_Tag_I, CKSEG0 | offset);
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ehb();
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data = read_c0_taglo();
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ehb();
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write_c0_errctl(errctl);
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ehb();
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return data;
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}
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static void dspram_store_tag(unsigned int offset, unsigned int data)
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{
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unsigned int errctl;
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/* enable SPRAM tag access */
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errctl = bis_c0_errctl(ERRCTL_SPRAM);
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ehb();
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write_c0_dtaglo(data);
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ehb();
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cache_op(Index_Store_Tag_D, CKSEG0 | offset);
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ehb();
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write_c0_errctl(errctl);
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ehb();
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}
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static unsigned int dspram_load_tag(unsigned int offset)
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{
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unsigned int data;
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unsigned int errctl;
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errctl = bis_c0_errctl(ERRCTL_SPRAM);
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ehb();
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cache_op(Index_Load_Tag_D, CKSEG0 | offset);
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ehb();
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data = read_c0_dtaglo();
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ehb();
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write_c0_errctl(errctl);
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ehb();
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return data;
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}
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static void probe_spram(char *type,
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unsigned int base,
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unsigned int (*read)(unsigned int),
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void (*write)(unsigned int, unsigned int))
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{
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unsigned int firstsize = 0, lastsize = 0;
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unsigned int firstpa = 0, lastpa = 0, pa = 0;
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unsigned int offset = 0;
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unsigned int size, tag0, tag1;
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unsigned int enabled;
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int i;
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/*
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* The limit is arbitrary but avoids the loop running away if
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* the SPRAM tags are implemented differently
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*/
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for (i = 0; i < 8; i++) {
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tag0 = read(offset);
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tag1 = read(offset+SPRAM_TAG_STRIDE);
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pr_debug("DBG %s%d: tag0=%08x tag1=%08x\n",
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type, i, tag0, tag1);
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size = tag1 & SPRAM_TAG1_SIZE_MASK;
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if (size == 0)
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break;
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if (i != 0) {
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/* tags may repeat... */
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if ((pa == firstpa && size == firstsize) ||
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(pa == lastpa && size == lastsize))
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break;
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}
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/* Align base with size */
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base = (base + size - 1) & ~(size-1);
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/* reprogram the base address base address and enable */
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tag0 = (base & SPRAM_TAG0_PA_MASK) | SPRAM_TAG0_ENABLE;
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write(offset, tag0);
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base += size;
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/* reread the tag */
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tag0 = read(offset);
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pa = tag0 & SPRAM_TAG0_PA_MASK;
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enabled = tag0 & SPRAM_TAG0_ENABLE;
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if (i == 0) {
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firstpa = pa;
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firstsize = size;
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}
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lastpa = pa;
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lastsize = size;
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if (strcmp(type, "DSPRAM") == 0) {
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unsigned int *vp = (unsigned int *)(CKSEG1 | pa);
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unsigned int v;
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#define TDAT 0x5a5aa5a5
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vp[0] = TDAT;
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vp[1] = ~TDAT;
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mb();
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v = vp[0];
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if (v != TDAT)
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printk(KERN_ERR "vp=%p wrote=%08x got=%08x\n",
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vp, TDAT, v);
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v = vp[1];
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if (v != ~TDAT)
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printk(KERN_ERR "vp=%p wrote=%08x got=%08x\n",
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vp+1, ~TDAT, v);
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}
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pr_info("%s%d: PA=%08x,Size=%08x%s\n",
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type, i, pa, size, enabled ? ",enabled" : "");
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offset += 2 * SPRAM_TAG_STRIDE;
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}
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}
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void spram_config(void)
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{
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unsigned int config0;
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switch (current_cpu_type()) {
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case CPU_24K:
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case CPU_34K:
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case CPU_74K:
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case CPU_1004K:
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case CPU_1074K:
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case CPU_INTERAPTIV:
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case CPU_PROAPTIV:
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case CPU_P5600:
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case CPU_QEMU_GENERIC:
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case CPU_I6400:
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config0 = read_c0_config();
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/* FIXME: addresses are Malta specific */
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if (config0 & (1<<24)) {
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probe_spram("ISPRAM", 0x1c000000,
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&ispram_load_tag, &ispram_store_tag);
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}
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if (config0 & (1<<23))
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probe_spram("DSPRAM", 0x1c100000,
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&dspram_load_tag, &dspram_store_tag);
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}
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}
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