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07f08d9cee
Rockchip SoCs use 2 different numbering schemes. Where the gpio- controllers just count 0-31 for their 32 gpios, the underlying iomux controller splits these into 4 separate entities A-D. Device-schematics always use these iomux-values to identify pins, so to make mapping schematics to devicetree easier Andy Yan introduced named constants for the pins but so far we only used them on new additions. Using a sed-script created by Emil Renner Berthing bulk-convert the remaining raw gpio numbers into their descriptive counterparts and also gets rid of the unhelpful RK_FUNC_x -> x and RK_GPIOx -> x mappings: /rockchip,pins *=/bcheck b # to end of script :append-next-line N :check /^[^;]*$/bappend-next-line s/<RK_GPIO\([0-9]\) /<\1 /g s/<\([^ ][^ ]* *\)0 /<\1RK_PA0 /g s/<\([^ ][^ ]* *\)1 /<\1RK_PA1 /g s/<\([^ ][^ ]* *\)2 /<\1RK_PA2 /g s/<\([^ ][^ ]* *\)3 /<\1RK_PA3 /g s/<\([^ ][^ ]* *\)4 /<\1RK_PA4 /g s/<\([^ ][^ ]* *\)5 /<\1RK_PA5 /g s/<\([^ ][^ ]* *\)6 /<\1RK_PA6 /g s/<\([^ ][^ ]* *\)7 /<\1RK_PA7 /g s/<\([^ ][^ ]* *\)8 /<\1RK_PB0 /g s/<\([^ ][^ ]* *\)9 /<\1RK_PB1 /g s/<\([^ ][^ ]* *\)10 /<\1RK_PB2 /g s/<\([^ ][^ ]* *\)11 /<\1RK_PB3 /g s/<\([^ ][^ ]* *\)12 /<\1RK_PB4 /g s/<\([^ ][^ ]* *\)13 /<\1RK_PB5 /g s/<\([^ ][^ ]* *\)14 /<\1RK_PB6 /g s/<\([^ ][^ ]* *\)15 /<\1RK_PB7 /g s/<\([^ ][^ ]* *\)16 /<\1RK_PC0 /g s/<\([^ ][^ ]* *\)17 /<\1RK_PC1 /g s/<\([^ ][^ ]* *\)18 /<\1RK_PC2 /g s/<\([^ ][^ ]* *\)19 /<\1RK_PC3 /g s/<\([^ ][^ ]* *\)20 /<\1RK_PC4 /g s/<\([^ ][^ ]* *\)21 /<\1RK_PC5 /g s/<\([^ ][^ ]* *\)22 /<\1RK_PC6 /g s/<\([^ ][^ ]* *\)23 /<\1RK_PC7 /g s/<\([^ ][^ ]* *\)24 /<\1RK_PD0 /g s/<\([^ ][^ ]* *\)25 /<\1RK_PD1 /g s/<\([^ ][^ ]* *\)26 /<\1RK_PD2 /g s/<\([^ ][^ ]* *\)27 /<\1RK_PD3 /g s/<\([^ ][^ ]* *\)28 /<\1RK_PD4 /g s/<\([^ ][^ ]* *\)29 /<\1RK_PD5 /g s/<\([^ ][^ ]* *\)30 /<\1RK_PD6 /g s/<\([^ ][^ ]* *\)31 /<\1RK_PD7 /g s/<\([^ ][^ ]* *[^ ][^ ]* *\)0 /<\1RK_FUNC_GPIO /g s/<\([^ ][^ ]* *[^ ][^ ]* *\)RK_FUNC_\([1-9]\) /<\1\2 /g Suggested-by: Emil Renner Berthing <esmil@mailme.dk> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
99 lines
1.9 KiB
Plaintext
99 lines
1.9 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Google Veyron Pinky Rev 2 board device tree source
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*
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* Copyright 2015 Google, Inc
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*/
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/dts-v1/;
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#include "rk3288-veyron-chromebook.dtsi"
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#include "cros-ec-sbs.dtsi"
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/ {
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model = "Google Pinky";
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compatible = "google,veyron-pinky-rev2", "google,veyron-pinky",
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"google,veyron", "rockchip,rk3288";
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/delete-node/emmc-pwrseq;
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};
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&emmc {
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/*
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* Use a pullup instead of a drive since the output is 3.3V and
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* really should be 1.8V (oops). The external pulldown will help
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* bring the voltage down if we only drive with a pullup here.
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* Therefore disable the powerseq (and actual reset) for pinky.
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*/
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/delete-property/mmc-pwrseq;
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pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_reset>;
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};
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&edp {
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/delete-property/pinctrl-names;
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/delete-property/pinctrl-0;
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force-hpd;
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};
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&gpio_keys {
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pinctrl-0 = <&pwr_key_h &ap_lid_int_l>;
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power {
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gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
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};
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};
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/* Touchpad connector */
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&i2c3 {
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status = "okay";
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clock-frequency = <400000>;
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i2c-scl-falling-time-ns = <50>;
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i2c-scl-rising-time-ns = <300>;
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};
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&pinctrl {
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buttons {
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pwr_key_h: pwr-key-h {
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rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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emmc {
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emmc_reset: emmc-reset {
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rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
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};
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};
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sdmmc {
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sdmmc_wp_gpio: sdmmc-wp-gpio {
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rockchip,pins = <7 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
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};
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};
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};
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&rk808 {
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regulators {
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vcc18_lcd: SWITCH_REG2 {
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regulator-always-on;
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regulator-boot-on;
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regulator-name = "vcc18_lcd";
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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};
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};
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&sdmmc {
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pinctrl-names = "default";
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pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
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&sdmmc_wp_gpio &sdmmc_bus4>;
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wp-gpios = <&gpio7 RK_PB2 GPIO_ACTIVE_HIGH>;
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};
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&tsadc {
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/* Some connection is flaky making the tsadc hang the system */
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status = "disabled";
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};
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