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29dcc60f6a
Add the first handler for #VC exceptions. At stage 1 there is no GHCB yet because the kernel might still be running on the EFI page table. The stage 1 handler is limited to the MSR-based protocol to talk to the hypervisor and can only support CPUID exit-codes, but that is enough to get to stage 2. [ bp: Zap superfluous newlines after rd/wrmsr instruction mnemonics. ] Signed-off-by: Joerg Roedel <jroedel@suse.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20200907131613.12703-20-joro@8bytes.org
33 lines
1.3 KiB
C
33 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_TRAPNR_H
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#define _ASM_X86_TRAPNR_H
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/* Interrupts/Exceptions */
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#define X86_TRAP_DE 0 /* Divide-by-zero */
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#define X86_TRAP_DB 1 /* Debug */
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#define X86_TRAP_NMI 2 /* Non-maskable Interrupt */
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#define X86_TRAP_BP 3 /* Breakpoint */
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#define X86_TRAP_OF 4 /* Overflow */
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#define X86_TRAP_BR 5 /* Bound Range Exceeded */
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#define X86_TRAP_UD 6 /* Invalid Opcode */
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#define X86_TRAP_NM 7 /* Device Not Available */
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#define X86_TRAP_DF 8 /* Double Fault */
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#define X86_TRAP_OLD_MF 9 /* Coprocessor Segment Overrun */
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#define X86_TRAP_TS 10 /* Invalid TSS */
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#define X86_TRAP_NP 11 /* Segment Not Present */
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#define X86_TRAP_SS 12 /* Stack Segment Fault */
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#define X86_TRAP_GP 13 /* General Protection Fault */
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#define X86_TRAP_PF 14 /* Page Fault */
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#define X86_TRAP_SPURIOUS 15 /* Spurious Interrupt */
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#define X86_TRAP_MF 16 /* x87 Floating-Point Exception */
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#define X86_TRAP_AC 17 /* Alignment Check */
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#define X86_TRAP_MC 18 /* Machine Check */
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#define X86_TRAP_XF 19 /* SIMD Floating-Point Exception */
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#define X86_TRAP_VE 20 /* Virtualization Exception */
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#define X86_TRAP_CP 21 /* Control Protection Exception */
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#define X86_TRAP_VC 29 /* VMM Communication Exception */
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#define X86_TRAP_IRET 32 /* IRET Exception */
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#endif
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