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QM is a general IP used by HiSilicon accelerators. It provides a general PCIe interface for the CPU and the accelerator to share a group of queues. A QM integrated in an accelerator provides queue management service. Queues can be assigned to PF and VFs, and queues can be controlled by unified mailboxes and doorbells. Specific task request are descripted by specific description buffer, which will be controlled and pass to related accelerator IP by QM. This patch adds a QM driver used by the accelerator driver to access the QM hardware. Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Kenneth Lee <liguozhu@hisilicon.com> Signed-off-by: Shiju Jose <shiju.jose@huawei.com> Signed-off-by: Hao Fang <fanghao11@huawei.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: John Garry <john.garry@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
22 lines
601 B
Plaintext
22 lines
601 B
Plaintext
# SPDX-License-Identifier: GPL-2.0
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config CRYPTO_DEV_HISI_SEC
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tristate "Support for Hisilicon SEC crypto block cipher accelerator"
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select CRYPTO_BLKCIPHER
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select CRYPTO_ALGAPI
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select SG_SPLIT
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depends on ARM64 || COMPILE_TEST
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depends on HAS_IOMEM
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help
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Support for Hisilicon SEC Engine in Hip06 and Hip07
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To compile this as a module, choose M here: the module
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will be called hisi_sec.
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config CRYPTO_DEV_HISI_QM
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tristate
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depends on ARM64 && PCI && PCI_MSI
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help
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HiSilicon accelerator engines use a common queue management
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interface. Specific engine driver may use this module.
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