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e6a6e5ad17
We cannot keep this in plat/common.h for common zImage support. Signed-off-by: Tony Lindgren <tony@atomide.com>
136 lines
4.3 KiB
C
136 lines
4.3 KiB
C
/*
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* AM33XX PRM functions
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*
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* Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include "../plat-omap/common.h"
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#include "common.h"
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#include "prm33xx.h"
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#include "prm-regbits-33xx.h"
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/* Read a register in a PRM instance */
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u32 am33xx_prm_read_reg(s16 inst, u16 idx)
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{
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return __raw_readl(prm_base + inst + idx);
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}
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/* Write into a register in a PRM instance */
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void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx)
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{
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__raw_writel(val, prm_base + inst + idx);
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}
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/* Read-modify-write a register in PRM. Caller must lock */
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u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)
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{
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u32 v;
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v = am33xx_prm_read_reg(inst, idx);
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v &= ~mask;
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v |= bits;
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am33xx_prm_write_reg(v, inst, idx);
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return v;
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}
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/**
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* am33xx_prm_is_hardreset_asserted - read the HW reset line state of
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* submodules contained in the hwmod module
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* @shift: register bit shift corresponding to the reset line to check
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* @inst: CM instance register offset (*_INST macro)
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* @rstctrl_offs: RM_RSTCTRL register address offset for this module
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*
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* Returns 1 if the (sub)module hardreset line is currently asserted,
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* 0 if the (sub)module hardreset line is not currently asserted, or
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* -EINVAL upon parameter error.
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*/
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int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst, u16 rstctrl_offs)
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{
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u32 v;
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v = am33xx_prm_read_reg(inst, rstctrl_offs);
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v &= 1 << shift;
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v >>= shift;
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return v;
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}
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/**
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* am33xx_prm_assert_hardreset - assert the HW reset line of a submodule
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* @shift: register bit shift corresponding to the reset line to assert
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* @inst: CM instance register offset (*_INST macro)
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* @rstctrl_reg: RM_RSTCTRL register address for this module
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*
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* Some IPs like dsp, ipu or iva contain processors that require an HW
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* reset line to be asserted / deasserted in order to fully enable the
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* IP. These modules may have multiple hard-reset lines that reset
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* different 'submodules' inside the IP block. This function will
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* place the submodule into reset. Returns 0 upon success or -EINVAL
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* upon an argument error.
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*/
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int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs)
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{
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u32 mask = 1 << shift;
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am33xx_prm_rmw_reg_bits(mask, mask, inst, rstctrl_offs);
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return 0;
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}
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/**
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* am33xx_prm_deassert_hardreset - deassert a submodule hardreset line and
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* wait
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* @shift: register bit shift corresponding to the reset line to deassert
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* @inst: CM instance register offset (*_INST macro)
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* @rstctrl_reg: RM_RSTCTRL register address for this module
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* @rstst_reg: RM_RSTST register address for this module
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*
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* Some IPs like dsp, ipu or iva contain processors that require an HW
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* reset line to be asserted / deasserted in order to fully enable the
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* IP. These modules may have multiple hard-reset lines that reset
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* different 'submodules' inside the IP block. This function will
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* take the submodule out of reset and wait until the PRCM indicates
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* that the reset has completed before returning. Returns 0 upon success or
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* -EINVAL upon an argument error, -EEXIST if the submodule was already out
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* of reset, or -EBUSY if the submodule did not exit reset promptly.
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*/
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int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
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u16 rstctrl_offs, u16 rstst_offs)
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{
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int c;
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u32 mask = 1 << shift;
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/* Check the current status to avoid de-asserting the line twice */
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if (am33xx_prm_is_hardreset_asserted(shift, inst, rstctrl_offs) == 0)
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return -EEXIST;
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/* Clear the reset status by writing 1 to the status bit */
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am33xx_prm_rmw_reg_bits(0xffffffff, mask, inst, rstst_offs);
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/* de-assert the reset control line */
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am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs);
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/* wait the status to be set */
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omap_test_timeout(am33xx_prm_is_hardreset_asserted(shift, inst,
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rstst_offs),
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MAX_MODULE_HARDRESET_WAIT, c);
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return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
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}
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