mirror of
https://github.com/edk2-porting/linux-next.git
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66b7e504c0
All this code is needed to properly initialize the 460EX PCIe host bridge(s). We re-initialize all ports again, even though this has been done in the bootloader (U-Boot) before. This way we make sure, that we always run the latest init code in Linux and don't depend on code versions from U-Boot. Unfortunately all IBM/AMCC chips currently supported in this PCIe driver need a different reset-/init-sequence. Tested on AMCC Canyonlands eval board. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
429 lines
12 KiB
C
429 lines
12 KiB
C
/*
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* PCI / PCI-X / PCI-Express support for 4xx parts
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*
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* Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
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*
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* Bits and pieces extracted from arch/ppc support by
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*
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* Matt Porter <mporter@kernel.crashing.org>
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*
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* Copyright 2002-2005 MontaVista Software Inc.
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*/
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#ifndef __PPC4XX_PCI_H__
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#define __PPC4XX_PCI_H__
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/*
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* 4xx PCI-X bridge register definitions
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*/
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#define PCIX0_VENDID 0x000
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#define PCIX0_DEVID 0x002
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#define PCIX0_COMMAND 0x004
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#define PCIX0_STATUS 0x006
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#define PCIX0_REVID 0x008
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#define PCIX0_CLS 0x009
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#define PCIX0_CACHELS 0x00c
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#define PCIX0_LATTIM 0x00d
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#define PCIX0_HDTYPE 0x00e
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#define PCIX0_BIST 0x00f
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#define PCIX0_BAR0L 0x010
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#define PCIX0_BAR0H 0x014
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#define PCIX0_BAR1 0x018
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#define PCIX0_BAR2L 0x01c
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#define PCIX0_BAR2H 0x020
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#define PCIX0_BAR3 0x024
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#define PCIX0_CISPTR 0x028
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#define PCIX0_SBSYSVID 0x02c
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#define PCIX0_SBSYSID 0x02e
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#define PCIX0_EROMBA 0x030
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#define PCIX0_CAP 0x034
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#define PCIX0_RES0 0x035
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#define PCIX0_RES1 0x036
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#define PCIX0_RES2 0x038
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#define PCIX0_INTLN 0x03c
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#define PCIX0_INTPN 0x03d
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#define PCIX0_MINGNT 0x03e
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#define PCIX0_MAXLTNCY 0x03f
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#define PCIX0_BRDGOPT1 0x040
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#define PCIX0_BRDGOPT2 0x044
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#define PCIX0_ERREN 0x050
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#define PCIX0_ERRSTS 0x054
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#define PCIX0_PLBBESR 0x058
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#define PCIX0_PLBBEARL 0x05c
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#define PCIX0_PLBBEARH 0x060
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#define PCIX0_POM0LAL 0x068
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#define PCIX0_POM0LAH 0x06c
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#define PCIX0_POM0SA 0x070
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#define PCIX0_POM0PCIAL 0x074
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#define PCIX0_POM0PCIAH 0x078
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#define PCIX0_POM1LAL 0x07c
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#define PCIX0_POM1LAH 0x080
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#define PCIX0_POM1SA 0x084
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#define PCIX0_POM1PCIAL 0x088
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#define PCIX0_POM1PCIAH 0x08c
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#define PCIX0_POM2SA 0x090
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#define PCIX0_PIM0SAL 0x098
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#define PCIX0_PIM0SA PCIX0_PIM0SAL
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#define PCIX0_PIM0LAL 0x09c
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#define PCIX0_PIM0LAH 0x0a0
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#define PCIX0_PIM1SA 0x0a4
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#define PCIX0_PIM1LAL 0x0a8
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#define PCIX0_PIM1LAH 0x0ac
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#define PCIX0_PIM2SAL 0x0b0
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#define PCIX0_PIM2SA PCIX0_PIM2SAL
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#define PCIX0_PIM2LAL 0x0b4
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#define PCIX0_PIM2LAH 0x0b8
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#define PCIX0_OMCAPID 0x0c0
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#define PCIX0_OMNIPTR 0x0c1
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#define PCIX0_OMMC 0x0c2
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#define PCIX0_OMMA 0x0c4
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#define PCIX0_OMMUA 0x0c8
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#define PCIX0_OMMDATA 0x0cc
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#define PCIX0_OMMEOI 0x0ce
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#define PCIX0_PMCAPID 0x0d0
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#define PCIX0_PMNIPTR 0x0d1
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#define PCIX0_PMC 0x0d2
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#define PCIX0_PMCSR 0x0d4
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#define PCIX0_PMCSRBSE 0x0d6
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#define PCIX0_PMDATA 0x0d7
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#define PCIX0_PMSCRR 0x0d8
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#define PCIX0_CAPID 0x0dc
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#define PCIX0_NIPTR 0x0dd
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#define PCIX0_CMD 0x0de
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#define PCIX0_STS 0x0e0
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#define PCIX0_IDR 0x0e4
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#define PCIX0_CID 0x0e8
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#define PCIX0_RID 0x0ec
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#define PCIX0_PIM0SAH 0x0f8
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#define PCIX0_PIM2SAH 0x0fc
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#define PCIX0_MSGIL 0x100
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#define PCIX0_MSGIH 0x104
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#define PCIX0_MSGOL 0x108
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#define PCIX0_MSGOH 0x10c
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#define PCIX0_IM 0x1f8
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/*
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* 4xx PCI bridge register definitions
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*/
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#define PCIL0_PMM0LA 0x00
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#define PCIL0_PMM0MA 0x04
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#define PCIL0_PMM0PCILA 0x08
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#define PCIL0_PMM0PCIHA 0x0c
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#define PCIL0_PMM1LA 0x10
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#define PCIL0_PMM1MA 0x14
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#define PCIL0_PMM1PCILA 0x18
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#define PCIL0_PMM1PCIHA 0x1c
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#define PCIL0_PMM2LA 0x20
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#define PCIL0_PMM2MA 0x24
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#define PCIL0_PMM2PCILA 0x28
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#define PCIL0_PMM2PCIHA 0x2c
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#define PCIL0_PTM1MS 0x30
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#define PCIL0_PTM1LA 0x34
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#define PCIL0_PTM2MS 0x38
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#define PCIL0_PTM2LA 0x3c
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/*
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* 4xx PCIe bridge register definitions
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*/
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/* DCR offsets */
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#define DCRO_PEGPL_CFGBAH 0x00
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#define DCRO_PEGPL_CFGBAL 0x01
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#define DCRO_PEGPL_CFGMSK 0x02
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#define DCRO_PEGPL_MSGBAH 0x03
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#define DCRO_PEGPL_MSGBAL 0x04
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#define DCRO_PEGPL_MSGMSK 0x05
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#define DCRO_PEGPL_OMR1BAH 0x06
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#define DCRO_PEGPL_OMR1BAL 0x07
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#define DCRO_PEGPL_OMR1MSKH 0x08
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#define DCRO_PEGPL_OMR1MSKL 0x09
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#define DCRO_PEGPL_OMR2BAH 0x0a
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#define DCRO_PEGPL_OMR2BAL 0x0b
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#define DCRO_PEGPL_OMR2MSKH 0x0c
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#define DCRO_PEGPL_OMR2MSKL 0x0d
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#define DCRO_PEGPL_OMR3BAH 0x0e
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#define DCRO_PEGPL_OMR3BAL 0x0f
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#define DCRO_PEGPL_OMR3MSKH 0x10
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#define DCRO_PEGPL_OMR3MSKL 0x11
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#define DCRO_PEGPL_REGBAH 0x12
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#define DCRO_PEGPL_REGBAL 0x13
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#define DCRO_PEGPL_REGMSK 0x14
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#define DCRO_PEGPL_SPECIAL 0x15
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#define DCRO_PEGPL_CFG 0x16
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#define DCRO_PEGPL_ESR 0x17
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#define DCRO_PEGPL_EARH 0x18
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#define DCRO_PEGPL_EARL 0x19
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#define DCRO_PEGPL_EATR 0x1a
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/* DMER mask */
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#define GPL_DMER_MASK_DISA 0x02000000
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/*
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* System DCRs (SDRs)
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*/
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#define PESDR0_PLLLCT1 0x03a0
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#define PESDR0_PLLLCT2 0x03a1
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#define PESDR0_PLLLCT3 0x03a2
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/*
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* 440SPe additional DCRs
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*/
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#define PESDR0_440SPE_UTLSET1 0x0300
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#define PESDR0_440SPE_UTLSET2 0x0301
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#define PESDR0_440SPE_DLPSET 0x0302
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#define PESDR0_440SPE_LOOP 0x0303
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#define PESDR0_440SPE_RCSSET 0x0304
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#define PESDR0_440SPE_RCSSTS 0x0305
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#define PESDR0_440SPE_HSSL0SET1 0x0306
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#define PESDR0_440SPE_HSSL0SET2 0x0307
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#define PESDR0_440SPE_HSSL0STS 0x0308
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#define PESDR0_440SPE_HSSL1SET1 0x0309
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#define PESDR0_440SPE_HSSL1SET2 0x030a
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#define PESDR0_440SPE_HSSL1STS 0x030b
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#define PESDR0_440SPE_HSSL2SET1 0x030c
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#define PESDR0_440SPE_HSSL2SET2 0x030d
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#define PESDR0_440SPE_HSSL2STS 0x030e
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#define PESDR0_440SPE_HSSL3SET1 0x030f
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#define PESDR0_440SPE_HSSL3SET2 0x0310
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#define PESDR0_440SPE_HSSL3STS 0x0311
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#define PESDR0_440SPE_HSSL4SET1 0x0312
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#define PESDR0_440SPE_HSSL4SET2 0x0313
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#define PESDR0_440SPE_HSSL4STS 0x0314
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#define PESDR0_440SPE_HSSL5SET1 0x0315
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#define PESDR0_440SPE_HSSL5SET2 0x0316
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#define PESDR0_440SPE_HSSL5STS 0x0317
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#define PESDR0_440SPE_HSSL6SET1 0x0318
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#define PESDR0_440SPE_HSSL6SET2 0x0319
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#define PESDR0_440SPE_HSSL6STS 0x031a
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#define PESDR0_440SPE_HSSL7SET1 0x031b
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#define PESDR0_440SPE_HSSL7SET2 0x031c
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#define PESDR0_440SPE_HSSL7STS 0x031d
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#define PESDR0_440SPE_HSSCTLSET 0x031e
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#define PESDR0_440SPE_LANE_ABCD 0x031f
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#define PESDR0_440SPE_LANE_EFGH 0x0320
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#define PESDR1_440SPE_UTLSET1 0x0340
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#define PESDR1_440SPE_UTLSET2 0x0341
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#define PESDR1_440SPE_DLPSET 0x0342
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#define PESDR1_440SPE_LOOP 0x0343
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#define PESDR1_440SPE_RCSSET 0x0344
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#define PESDR1_440SPE_RCSSTS 0x0345
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#define PESDR1_440SPE_HSSL0SET1 0x0346
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#define PESDR1_440SPE_HSSL0SET2 0x0347
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#define PESDR1_440SPE_HSSL0STS 0x0348
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#define PESDR1_440SPE_HSSL1SET1 0x0349
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#define PESDR1_440SPE_HSSL1SET2 0x034a
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#define PESDR1_440SPE_HSSL1STS 0x034b
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#define PESDR1_440SPE_HSSL2SET1 0x034c
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#define PESDR1_440SPE_HSSL2SET2 0x034d
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#define PESDR1_440SPE_HSSL2STS 0x034e
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#define PESDR1_440SPE_HSSL3SET1 0x034f
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#define PESDR1_440SPE_HSSL3SET2 0x0350
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#define PESDR1_440SPE_HSSL3STS 0x0351
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#define PESDR1_440SPE_HSSCTLSET 0x0352
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#define PESDR1_440SPE_LANE_ABCD 0x0353
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#define PESDR2_440SPE_UTLSET1 0x0370
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#define PESDR2_440SPE_UTLSET2 0x0371
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#define PESDR2_440SPE_DLPSET 0x0372
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#define PESDR2_440SPE_LOOP 0x0373
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#define PESDR2_440SPE_RCSSET 0x0374
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#define PESDR2_440SPE_RCSSTS 0x0375
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#define PESDR2_440SPE_HSSL0SET1 0x0376
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#define PESDR2_440SPE_HSSL0SET2 0x0377
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#define PESDR2_440SPE_HSSL0STS 0x0378
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#define PESDR2_440SPE_HSSL1SET1 0x0379
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#define PESDR2_440SPE_HSSL1SET2 0x037a
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#define PESDR2_440SPE_HSSL1STS 0x037b
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#define PESDR2_440SPE_HSSL2SET1 0x037c
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#define PESDR2_440SPE_HSSL2SET2 0x037d
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#define PESDR2_440SPE_HSSL2STS 0x037e
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#define PESDR2_440SPE_HSSL3SET1 0x037f
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#define PESDR2_440SPE_HSSL3SET2 0x0380
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#define PESDR2_440SPE_HSSL3STS 0x0381
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#define PESDR2_440SPE_HSSCTLSET 0x0382
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#define PESDR2_440SPE_LANE_ABCD 0x0383
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/*
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* 405EX additional DCRs
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*/
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#define PESDR0_405EX_UTLSET1 0x0400
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#define PESDR0_405EX_UTLSET2 0x0401
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#define PESDR0_405EX_DLPSET 0x0402
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#define PESDR0_405EX_LOOP 0x0403
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#define PESDR0_405EX_RCSSET 0x0404
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#define PESDR0_405EX_RCSSTS 0x0405
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#define PESDR0_405EX_PHYSET1 0x0406
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#define PESDR0_405EX_PHYSET2 0x0407
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#define PESDR0_405EX_BIST 0x0408
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#define PESDR0_405EX_LPB 0x040B
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#define PESDR0_405EX_PHYSTA 0x040C
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#define PESDR1_405EX_UTLSET1 0x0440
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#define PESDR1_405EX_UTLSET2 0x0441
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#define PESDR1_405EX_DLPSET 0x0442
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#define PESDR1_405EX_LOOP 0x0443
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#define PESDR1_405EX_RCSSET 0x0444
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#define PESDR1_405EX_RCSSTS 0x0445
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#define PESDR1_405EX_PHYSET1 0x0446
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#define PESDR1_405EX_PHYSET2 0x0447
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#define PESDR1_405EX_BIST 0x0448
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#define PESDR1_405EX_LPB 0x044B
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#define PESDR1_405EX_PHYSTA 0x044C
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/*
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* 460EX additional DCRs
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*/
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#define PESDR0_460EX_L0BIST 0x0308
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#define PESDR0_460EX_L0BISTSTS 0x0309
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#define PESDR0_460EX_L0CDRCTL 0x030A
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#define PESDR0_460EX_L0DRV 0x030B
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#define PESDR0_460EX_L0REC 0x030C
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#define PESDR0_460EX_L0LPB 0x030D
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#define PESDR0_460EX_L0CLK 0x030E
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#define PESDR0_460EX_PHY_CTL_RST 0x030F
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#define PESDR0_460EX_RSTSTA 0x0310
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#define PESDR0_460EX_OBS 0x0311
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#define PESDR0_460EX_L0ERRC 0x0320
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#define PESDR1_460EX_L0BIST 0x0348
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#define PESDR1_460EX_L1BIST 0x0349
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#define PESDR1_460EX_L2BIST 0x034A
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#define PESDR1_460EX_L3BIST 0x034B
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#define PESDR1_460EX_L0BISTSTS 0x034C
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#define PESDR1_460EX_L1BISTSTS 0x034D
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#define PESDR1_460EX_L2BISTSTS 0x034E
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#define PESDR1_460EX_L3BISTSTS 0x034F
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#define PESDR1_460EX_L0CDRCTL 0x0350
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#define PESDR1_460EX_L1CDRCTL 0x0351
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#define PESDR1_460EX_L2CDRCTL 0x0352
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#define PESDR1_460EX_L3CDRCTL 0x0353
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#define PESDR1_460EX_L0DRV 0x0354
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#define PESDR1_460EX_L1DRV 0x0355
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#define PESDR1_460EX_L2DRV 0x0356
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#define PESDR1_460EX_L3DRV 0x0357
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#define PESDR1_460EX_L0REC 0x0358
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#define PESDR1_460EX_L1REC 0x0359
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#define PESDR1_460EX_L2REC 0x035A
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#define PESDR1_460EX_L3REC 0x035B
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#define PESDR1_460EX_L0LPB 0x035C
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#define PESDR1_460EX_L1LPB 0x035D
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#define PESDR1_460EX_L2LPB 0x035E
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#define PESDR1_460EX_L3LPB 0x035F
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#define PESDR1_460EX_L0CLK 0x0360
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#define PESDR1_460EX_L1CLK 0x0361
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#define PESDR1_460EX_L2CLK 0x0362
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#define PESDR1_460EX_L3CLK 0x0363
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#define PESDR1_460EX_PHY_CTL_RST 0x0364
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#define PESDR1_460EX_RSTSTA 0x0365
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#define PESDR1_460EX_OBS 0x0366
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#define PESDR1_460EX_L0ERRC 0x0368
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#define PESDR1_460EX_L1ERRC 0x0369
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#define PESDR1_460EX_L2ERRC 0x036A
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#define PESDR1_460EX_L3ERRC 0x036B
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#define PESDR0_460EX_IHS1 0x036C
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#define PESDR0_460EX_IHS2 0x036D
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/*
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* Of the above, some are common offsets from the base
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*/
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#define PESDRn_UTLSET1 0x00
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#define PESDRn_UTLSET2 0x01
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#define PESDRn_DLPSET 0x02
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#define PESDRn_LOOP 0x03
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#define PESDRn_RCSSET 0x04
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#define PESDRn_RCSSTS 0x05
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/* 440spe only */
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#define PESDRn_440SPE_HSSL0SET1 0x06
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#define PESDRn_440SPE_HSSL0SET2 0x07
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#define PESDRn_440SPE_HSSL0STS 0x08
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#define PESDRn_440SPE_HSSL1SET1 0x09
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#define PESDRn_440SPE_HSSL1SET2 0x0a
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#define PESDRn_440SPE_HSSL1STS 0x0b
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#define PESDRn_440SPE_HSSL2SET1 0x0c
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#define PESDRn_440SPE_HSSL2SET2 0x0d
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#define PESDRn_440SPE_HSSL2STS 0x0e
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#define PESDRn_440SPE_HSSL3SET1 0x0f
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#define PESDRn_440SPE_HSSL3SET2 0x10
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#define PESDRn_440SPE_HSSL3STS 0x11
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/* 440spe port 0 only */
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#define PESDRn_440SPE_HSSL4SET1 0x12
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#define PESDRn_440SPE_HSSL4SET2 0x13
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#define PESDRn_440SPE_HSSL4STS 0x14
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#define PESDRn_440SPE_HSSL5SET1 0x15
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#define PESDRn_440SPE_HSSL5SET2 0x16
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#define PESDRn_440SPE_HSSL5STS 0x17
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#define PESDRn_440SPE_HSSL6SET1 0x18
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#define PESDRn_440SPE_HSSL6SET2 0x19
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#define PESDRn_440SPE_HSSL6STS 0x1a
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#define PESDRn_440SPE_HSSL7SET1 0x1b
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#define PESDRn_440SPE_HSSL7SET2 0x1c
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#define PESDRn_440SPE_HSSL7STS 0x1d
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/* 405ex only */
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#define PESDRn_405EX_PHYSET1 0x06
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#define PESDRn_405EX_PHYSET2 0x07
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#define PESDRn_405EX_PHYSTA 0x0c
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/*
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* UTL register offsets
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*/
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#define PEUTL_PBCTL 0x00
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#define PEUTL_PBBSZ 0x20
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#define PEUTL_OPDBSZ 0x68
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#define PEUTL_IPHBSZ 0x70
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#define PEUTL_IPDBSZ 0x78
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#define PEUTL_OUTTR 0x90
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#define PEUTL_INTR 0x98
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#define PEUTL_PCTL 0xa0
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#define PEUTL_RCSTA 0xB0
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#define PEUTL_RCIRQEN 0xb8
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/*
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* Config space register offsets
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*/
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#define PECFG_ECRTCTL 0x074
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#define PECFG_BAR0LMPA 0x210
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#define PECFG_BAR0HMPA 0x214
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#define PECFG_BAR1MPA 0x218
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#define PECFG_BAR2LMPA 0x220
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#define PECFG_BAR2HMPA 0x224
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#define PECFG_PIMEN 0x33c
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#define PECFG_PIM0LAL 0x340
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#define PECFG_PIM0LAH 0x344
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#define PECFG_PIM1LAL 0x348
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#define PECFG_PIM1LAH 0x34c
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#define PECFG_PIM01SAL 0x350
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#define PECFG_PIM01SAH 0x354
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#define PECFG_POM0LAL 0x380
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#define PECFG_POM0LAH 0x384
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#define PECFG_POM1LAL 0x388
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#define PECFG_POM1LAH 0x38c
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#define PECFG_POM2LAL 0x390
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#define PECFG_POM2LAH 0x394
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/* SDR Bit Mappings */
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#define PESDRx_RCSSET_HLDPLB 0x10000000
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#define PESDRx_RCSSET_RSTGU 0x01000000
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#define PESDRx_RCSSET_RDY 0x00100000
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#define PESDRx_RCSSET_RSTDL 0x00010000
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#define PESDRx_RCSSET_RSTPYN 0x00001000
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enum
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{
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PTYPE_ENDPOINT = 0x0,
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PTYPE_LEGACY_ENDPOINT = 0x1,
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PTYPE_ROOT_PORT = 0x4,
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LNKW_X1 = 0x1,
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LNKW_X4 = 0x4,
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LNKW_X8 = 0x8
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};
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#endif /* __PPC4XX_PCI_H__ */
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