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13cad9851e
The scheduler IPI does not need the full interrupt entry handling logic when the entry is from kernel mode. Use IDTENTRY_SYSVEC_SIMPLE and spare all the overhead. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@kernel.org> Acked-by: Andy Lutomirski <luto@kernel.org> Link: https://lore.kernel.org/r/20200521202119.835425642@linutronix.de
143 lines
3.0 KiB
C
143 lines
3.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_HW_IRQ_H
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#define _ASM_X86_HW_IRQ_H
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/*
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* (C) 1992, 1993 Linus Torvalds, (C) 1997 Ingo Molnar
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*
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* moved some of the old arch/i386/kernel/irq.h to here. VY
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*
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* IRQ/IPI changes taken from work by Thomas Radke
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* <tomsoft@informatik.tu-chemnitz.de>
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*
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* hacked by Andi Kleen for x86-64.
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* unified by tglx
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*/
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#include <asm/irq_vectors.h>
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#define IRQ_MATRIX_BITS NR_VECTORS
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#ifndef __ASSEMBLY__
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#include <linux/percpu.h>
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#include <linux/profile.h>
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#include <linux/smp.h>
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#include <linux/atomic.h>
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#include <asm/irq.h>
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#include <asm/sections.h>
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#ifdef CONFIG_X86_LOCAL_APIC
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struct irq_data;
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struct pci_dev;
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struct msi_desc;
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enum irq_alloc_type {
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X86_IRQ_ALLOC_TYPE_IOAPIC = 1,
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X86_IRQ_ALLOC_TYPE_HPET,
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X86_IRQ_ALLOC_TYPE_MSI,
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X86_IRQ_ALLOC_TYPE_MSIX,
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X86_IRQ_ALLOC_TYPE_DMAR,
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X86_IRQ_ALLOC_TYPE_UV,
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};
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struct irq_alloc_info {
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enum irq_alloc_type type;
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u32 flags;
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const struct cpumask *mask; /* CPU mask for vector allocation */
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union {
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int unused;
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#ifdef CONFIG_HPET_TIMER
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struct {
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int hpet_id;
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int hpet_index;
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void *hpet_data;
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};
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#endif
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#ifdef CONFIG_PCI_MSI
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struct {
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struct pci_dev *msi_dev;
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irq_hw_number_t msi_hwirq;
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};
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#endif
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#ifdef CONFIG_X86_IO_APIC
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struct {
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int ioapic_id;
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int ioapic_pin;
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int ioapic_node;
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u32 ioapic_trigger : 1;
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u32 ioapic_polarity : 1;
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u32 ioapic_valid : 1;
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struct IO_APIC_route_entry *ioapic_entry;
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};
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#endif
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#ifdef CONFIG_DMAR_TABLE
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struct {
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int dmar_id;
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void *dmar_data;
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};
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#endif
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#ifdef CONFIG_X86_UV
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struct {
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int uv_limit;
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int uv_blade;
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unsigned long uv_offset;
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char *uv_name;
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};
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#endif
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#if IS_ENABLED(CONFIG_VMD)
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struct {
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struct msi_desc *desc;
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};
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#endif
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};
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};
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struct irq_cfg {
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unsigned int dest_apicid;
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unsigned int vector;
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};
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extern struct irq_cfg *irq_cfg(unsigned int irq);
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extern struct irq_cfg *irqd_cfg(struct irq_data *irq_data);
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extern void lock_vector_lock(void);
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extern void unlock_vector_lock(void);
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#ifdef CONFIG_SMP
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extern void send_cleanup_vector(struct irq_cfg *);
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extern void irq_complete_move(struct irq_cfg *cfg);
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#else
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static inline void send_cleanup_vector(struct irq_cfg *c) { }
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static inline void irq_complete_move(struct irq_cfg *c) { }
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#endif
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extern void apic_ack_edge(struct irq_data *data);
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#else /* CONFIG_X86_LOCAL_APIC */
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static inline void lock_vector_lock(void) {}
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static inline void unlock_vector_lock(void) {}
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#endif /* CONFIG_X86_LOCAL_APIC */
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/* Statistics */
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extern atomic_t irq_err_count;
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extern atomic_t irq_mis_count;
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extern void elcr_set_level_irq(unsigned int irq);
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extern char irq_entries_start[];
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#ifdef CONFIG_TRACING
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#define trace_irq_entries_start irq_entries_start
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#endif
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extern char spurious_entries_start[];
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#define VECTOR_UNUSED NULL
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#define VECTOR_SHUTDOWN ((void *)-1L)
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#define VECTOR_RETRIGGERED ((void *)-2L)
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typedef struct irq_desc* vector_irq_t[NR_VECTORS];
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DECLARE_PER_CPU(vector_irq_t, vector_irq);
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#endif /* !ASSEMBLY_ */
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#endif /* _ASM_X86_HW_IRQ_H */
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