mirror of
https://github.com/edk2-porting/linux-next.git
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1a0483d2a4
This patch adds platform data and DT bindings to allow to overwrite the stored disabled state for each clock output. Signed-off-by: Marek Belisko <marek.belisko@streamunlimited.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
157 lines
5.3 KiB
C
157 lines
5.3 KiB
C
/*
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* clk-si5351.h: Silicon Laboratories Si5351A/B/C I2C Clock Generator
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*
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* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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* Rabeeh Khoury <rabeeh@solid-run.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef _CLK_SI5351_H_
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#define _CLK_SI5351_H_
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#define SI5351_BUS_BASE_ADDR 0x60
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#define SI5351_PLL_VCO_MIN 600000000
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#define SI5351_PLL_VCO_MAX 900000000
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#define SI5351_MULTISYNTH_MIN_FREQ 1000000
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#define SI5351_MULTISYNTH_DIVBY4_FREQ 150000000
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#define SI5351_MULTISYNTH_MAX_FREQ 160000000
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#define SI5351_MULTISYNTH67_MAX_FREQ SI5351_MULTISYNTH_DIVBY4_FREQ
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#define SI5351_CLKOUT_MIN_FREQ 8000
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#define SI5351_CLKOUT_MAX_FREQ SI5351_MULTISYNTH_MAX_FREQ
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#define SI5351_CLKOUT67_MAX_FREQ SI5351_MULTISYNTH67_MAX_FREQ
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#define SI5351_PLL_A_MIN 15
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#define SI5351_PLL_A_MAX 90
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#define SI5351_PLL_B_MAX (SI5351_PLL_C_MAX-1)
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#define SI5351_PLL_C_MAX 1048575
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#define SI5351_MULTISYNTH_A_MIN 6
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#define SI5351_MULTISYNTH_A_MAX 1800
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#define SI5351_MULTISYNTH67_A_MAX 254
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#define SI5351_MULTISYNTH_B_MAX (SI5351_MULTISYNTH_C_MAX-1)
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#define SI5351_MULTISYNTH_C_MAX 1048575
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#define SI5351_MULTISYNTH_P1_MAX ((1<<18)-1)
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#define SI5351_MULTISYNTH_P2_MAX ((1<<20)-1)
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#define SI5351_MULTISYNTH_P3_MAX ((1<<20)-1)
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#define SI5351_DEVICE_STATUS 0
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#define SI5351_INTERRUPT_STATUS 1
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#define SI5351_INTERRUPT_MASK 2
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#define SI5351_STATUS_SYS_INIT (1<<7)
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#define SI5351_STATUS_LOL_B (1<<6)
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#define SI5351_STATUS_LOL_A (1<<5)
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#define SI5351_STATUS_LOS (1<<4)
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#define SI5351_OUTPUT_ENABLE_CTRL 3
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#define SI5351_OEB_PIN_ENABLE_CTRL 9
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#define SI5351_PLL_INPUT_SOURCE 15
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#define SI5351_CLKIN_DIV_MASK (3<<6)
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#define SI5351_CLKIN_DIV_1 (0<<6)
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#define SI5351_CLKIN_DIV_2 (1<<6)
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#define SI5351_CLKIN_DIV_4 (2<<6)
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#define SI5351_CLKIN_DIV_8 (3<<6)
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#define SI5351_PLLB_SOURCE (1<<3)
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#define SI5351_PLLA_SOURCE (1<<2)
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#define SI5351_CLK0_CTRL 16
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#define SI5351_CLK1_CTRL 17
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#define SI5351_CLK2_CTRL 18
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#define SI5351_CLK3_CTRL 19
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#define SI5351_CLK4_CTRL 20
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#define SI5351_CLK5_CTRL 21
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#define SI5351_CLK6_CTRL 22
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#define SI5351_CLK7_CTRL 23
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#define SI5351_CLK_POWERDOWN (1<<7)
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#define SI5351_CLK_INTEGER_MODE (1<<6)
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#define SI5351_CLK_PLL_SELECT (1<<5)
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#define SI5351_CLK_INVERT (1<<4)
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#define SI5351_CLK_INPUT_MASK (3<<2)
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#define SI5351_CLK_INPUT_XTAL (0<<2)
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#define SI5351_CLK_INPUT_CLKIN (1<<2)
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#define SI5351_CLK_INPUT_MULTISYNTH_0_4 (2<<2)
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#define SI5351_CLK_INPUT_MULTISYNTH_N (3<<2)
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#define SI5351_CLK_DRIVE_STRENGTH_MASK (3<<0)
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#define SI5351_CLK_DRIVE_STRENGTH_2MA (0<<0)
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#define SI5351_CLK_DRIVE_STRENGTH_4MA (1<<0)
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#define SI5351_CLK_DRIVE_STRENGTH_6MA (2<<0)
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#define SI5351_CLK_DRIVE_STRENGTH_8MA (3<<0)
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#define SI5351_CLK3_0_DISABLE_STATE 24
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#define SI5351_CLK7_4_DISABLE_STATE 25
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#define SI5351_CLK_DISABLE_STATE_MASK 3
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#define SI5351_CLK_DISABLE_STATE_LOW 0
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#define SI5351_CLK_DISABLE_STATE_HIGH 1
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#define SI5351_CLK_DISABLE_STATE_FLOAT 2
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#define SI5351_CLK_DISABLE_STATE_NEVER 3
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#define SI5351_PARAMETERS_LENGTH 8
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#define SI5351_PLLA_PARAMETERS 26
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#define SI5351_PLLB_PARAMETERS 34
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#define SI5351_CLK0_PARAMETERS 42
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#define SI5351_CLK1_PARAMETERS 50
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#define SI5351_CLK2_PARAMETERS 58
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#define SI5351_CLK3_PARAMETERS 66
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#define SI5351_CLK4_PARAMETERS 74
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#define SI5351_CLK5_PARAMETERS 82
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#define SI5351_CLK6_PARAMETERS 90
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#define SI5351_CLK7_PARAMETERS 91
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#define SI5351_CLK6_7_OUTPUT_DIVIDER 92
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#define SI5351_OUTPUT_CLK_DIV_MASK (7 << 4)
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#define SI5351_OUTPUT_CLK6_DIV_MASK (7 << 0)
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#define SI5351_OUTPUT_CLK_DIV_SHIFT 4
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#define SI5351_OUTPUT_CLK_DIV6_SHIFT 0
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#define SI5351_OUTPUT_CLK_DIV_1 0
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#define SI5351_OUTPUT_CLK_DIV_2 1
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#define SI5351_OUTPUT_CLK_DIV_4 2
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#define SI5351_OUTPUT_CLK_DIV_8 3
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#define SI5351_OUTPUT_CLK_DIV_16 4
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#define SI5351_OUTPUT_CLK_DIV_32 5
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#define SI5351_OUTPUT_CLK_DIV_64 6
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#define SI5351_OUTPUT_CLK_DIV_128 7
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#define SI5351_OUTPUT_CLK_DIVBY4 (3<<2)
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#define SI5351_SSC_PARAM0 149
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#define SI5351_SSC_PARAM1 150
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#define SI5351_SSC_PARAM2 151
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#define SI5351_SSC_PARAM3 152
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#define SI5351_SSC_PARAM4 153
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#define SI5351_SSC_PARAM5 154
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#define SI5351_SSC_PARAM6 155
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#define SI5351_SSC_PARAM7 156
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#define SI5351_SSC_PARAM8 157
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#define SI5351_SSC_PARAM9 158
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#define SI5351_SSC_PARAM10 159
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#define SI5351_SSC_PARAM11 160
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#define SI5351_SSC_PARAM12 161
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#define SI5351_VXCO_PARAMETERS_LOW 162
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#define SI5351_VXCO_PARAMETERS_MID 163
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#define SI5351_VXCO_PARAMETERS_HIGH 164
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#define SI5351_CLK0_PHASE_OFFSET 165
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#define SI5351_CLK1_PHASE_OFFSET 166
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#define SI5351_CLK2_PHASE_OFFSET 167
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#define SI5351_CLK3_PHASE_OFFSET 168
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#define SI5351_CLK4_PHASE_OFFSET 169
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#define SI5351_CLK5_PHASE_OFFSET 170
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#define SI5351_PLL_RESET 177
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#define SI5351_PLL_RESET_B (1<<7)
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#define SI5351_PLL_RESET_A (1<<5)
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#define SI5351_CRYSTAL_LOAD 183
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#define SI5351_CRYSTAL_LOAD_MASK (3<<6)
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#define SI5351_CRYSTAL_LOAD_6PF (1<<6)
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#define SI5351_CRYSTAL_LOAD_8PF (2<<6)
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#define SI5351_CRYSTAL_LOAD_10PF (3<<6)
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#define SI5351_FANOUT_ENABLE 187
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#define SI5351_CLKIN_ENABLE (1<<7)
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#define SI5351_XTAL_ENABLE (1<<6)
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#define SI5351_MULTISYNTH_ENABLE (1<<4)
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#endif
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