mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-25 21:54:06 +08:00
843a85ced9
* pci/host-designware: PCI: designware: Remove unnecessary use of 'conf_lock' spinlock PCI: designware: Use new OF interrupt mapping when possible PCI: designware: Fix iATU programming for cfg1, io and mem viewport PCI: designware: Fix comment for setting number of lanes * pci/host-imx6: PCI: designware: Split Exynos and i.MX bindings * pci/host-mvebu: PCI: mvebu: Use '%pa' for printing 'phys_addr_t' type PCI: mvebu: Remove unnecessary use of 'conf_lock' spinlock PCI: mvebu: split PCIe BARs into multiple MBus windows when needed bus: mvebu-mbus: allow several windows with the same target/attribute bus: mvebu-mbus: Avoid setting an undefined window size PCI: mvebu: fix off-by-one in the computed size of the mbus windows * pci/host-tegra: PCI: tegra: Use new OF interrupt mapping when possible
668 lines
18 KiB
C
668 lines
18 KiB
C
/*
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* PCIe host controller driver for Samsung EXYNOS SoCs
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*
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* Copyright (C) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Author: Jingoo Han <jg1.han@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/gpio.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_gpio.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/resource.h>
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#include <linux/signal.h>
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#include <linux/types.h>
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#include "pcie-designware.h"
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#define to_exynos_pcie(x) container_of(x, struct exynos_pcie, pp)
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struct exynos_pcie {
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void __iomem *elbi_base;
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void __iomem *phy_base;
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void __iomem *block_base;
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int reset_gpio;
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struct clk *clk;
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struct clk *bus_clk;
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struct pcie_port pp;
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};
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/* PCIe ELBI registers */
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#define PCIE_IRQ_PULSE 0x000
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#define IRQ_INTA_ASSERT (0x1 << 0)
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#define IRQ_INTB_ASSERT (0x1 << 2)
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#define IRQ_INTC_ASSERT (0x1 << 4)
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#define IRQ_INTD_ASSERT (0x1 << 6)
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#define PCIE_IRQ_LEVEL 0x004
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#define PCIE_IRQ_SPECIAL 0x008
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#define PCIE_IRQ_EN_PULSE 0x00c
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#define PCIE_IRQ_EN_LEVEL 0x010
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#define IRQ_MSI_ENABLE (0x1 << 2)
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#define PCIE_IRQ_EN_SPECIAL 0x014
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#define PCIE_PWR_RESET 0x018
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#define PCIE_CORE_RESET 0x01c
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#define PCIE_CORE_RESET_ENABLE (0x1 << 0)
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#define PCIE_STICKY_RESET 0x020
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#define PCIE_NONSTICKY_RESET 0x024
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#define PCIE_APP_INIT_RESET 0x028
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#define PCIE_APP_LTSSM_ENABLE 0x02c
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#define PCIE_ELBI_RDLH_LINKUP 0x064
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#define PCIE_ELBI_LTSSM_ENABLE 0x1
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#define PCIE_ELBI_SLV_AWMISC 0x11c
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#define PCIE_ELBI_SLV_ARMISC 0x120
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#define PCIE_ELBI_SLV_DBI_ENABLE (0x1 << 21)
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/* PCIe Purple registers */
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#define PCIE_PHY_GLOBAL_RESET 0x000
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#define PCIE_PHY_COMMON_RESET 0x004
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#define PCIE_PHY_CMN_REG 0x008
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#define PCIE_PHY_MAC_RESET 0x00c
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#define PCIE_PHY_PLL_LOCKED 0x010
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#define PCIE_PHY_TRSVREG_RESET 0x020
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#define PCIE_PHY_TRSV_RESET 0x024
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/* PCIe PHY registers */
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#define PCIE_PHY_IMPEDANCE 0x004
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#define PCIE_PHY_PLL_DIV_0 0x008
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#define PCIE_PHY_PLL_BIAS 0x00c
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#define PCIE_PHY_DCC_FEEDBACK 0x014
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#define PCIE_PHY_PLL_DIV_1 0x05c
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#define PCIE_PHY_COMMON_POWER 0x064
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#define PCIE_PHY_COMMON_PD_CMN (0x1 << 3)
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#define PCIE_PHY_TRSV0_EMP_LVL 0x084
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#define PCIE_PHY_TRSV0_DRV_LVL 0x088
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#define PCIE_PHY_TRSV0_RXCDR 0x0ac
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#define PCIE_PHY_TRSV0_POWER 0x0c4
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#define PCIE_PHY_TRSV0_PD_TSV (0x1 << 7)
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#define PCIE_PHY_TRSV0_LVCC 0x0dc
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#define PCIE_PHY_TRSV1_EMP_LVL 0x144
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#define PCIE_PHY_TRSV1_RXCDR 0x16c
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#define PCIE_PHY_TRSV1_POWER 0x184
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#define PCIE_PHY_TRSV1_PD_TSV (0x1 << 7)
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#define PCIE_PHY_TRSV1_LVCC 0x19c
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#define PCIE_PHY_TRSV2_EMP_LVL 0x204
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#define PCIE_PHY_TRSV2_RXCDR 0x22c
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#define PCIE_PHY_TRSV2_POWER 0x244
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#define PCIE_PHY_TRSV2_PD_TSV (0x1 << 7)
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#define PCIE_PHY_TRSV2_LVCC 0x25c
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#define PCIE_PHY_TRSV3_EMP_LVL 0x2c4
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#define PCIE_PHY_TRSV3_RXCDR 0x2ec
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#define PCIE_PHY_TRSV3_POWER 0x304
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#define PCIE_PHY_TRSV3_PD_TSV (0x1 << 7)
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#define PCIE_PHY_TRSV3_LVCC 0x31c
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static inline void exynos_elb_writel(struct exynos_pcie *pcie, u32 val, u32 reg)
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{
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writel(val, pcie->elbi_base + reg);
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}
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static inline u32 exynos_elb_readl(struct exynos_pcie *pcie, u32 reg)
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{
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return readl(pcie->elbi_base + reg);
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}
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static inline void exynos_phy_writel(struct exynos_pcie *pcie, u32 val, u32 reg)
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{
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writel(val, pcie->phy_base + reg);
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}
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static inline u32 exynos_phy_readl(struct exynos_pcie *pcie, u32 reg)
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{
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return readl(pcie->phy_base + reg);
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}
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static inline void exynos_blk_writel(struct exynos_pcie *pcie, u32 val, u32 reg)
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{
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writel(val, pcie->block_base + reg);
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}
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static inline u32 exynos_blk_readl(struct exynos_pcie *pcie, u32 reg)
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{
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return readl(pcie->block_base + reg);
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}
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static void exynos_pcie_sideband_dbi_w_mode(struct pcie_port *pp, bool on)
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{
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u32 val;
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struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
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if (on) {
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val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_AWMISC);
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val |= PCIE_ELBI_SLV_DBI_ENABLE;
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exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_AWMISC);
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} else {
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val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_AWMISC);
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val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
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exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_AWMISC);
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}
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}
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static void exynos_pcie_sideband_dbi_r_mode(struct pcie_port *pp, bool on)
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{
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u32 val;
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struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
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if (on) {
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val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_ARMISC);
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val |= PCIE_ELBI_SLV_DBI_ENABLE;
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exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_ARMISC);
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} else {
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val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_ARMISC);
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val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
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exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_ARMISC);
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}
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}
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static void exynos_pcie_assert_core_reset(struct pcie_port *pp)
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{
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u32 val;
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struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
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val = exynos_elb_readl(exynos_pcie, PCIE_CORE_RESET);
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val &= ~PCIE_CORE_RESET_ENABLE;
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exynos_elb_writel(exynos_pcie, val, PCIE_CORE_RESET);
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exynos_elb_writel(exynos_pcie, 0, PCIE_PWR_RESET);
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exynos_elb_writel(exynos_pcie, 0, PCIE_STICKY_RESET);
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exynos_elb_writel(exynos_pcie, 0, PCIE_NONSTICKY_RESET);
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}
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static void exynos_pcie_deassert_core_reset(struct pcie_port *pp)
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{
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u32 val;
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struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
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val = exynos_elb_readl(exynos_pcie, PCIE_CORE_RESET);
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val |= PCIE_CORE_RESET_ENABLE;
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exynos_elb_writel(exynos_pcie, val, PCIE_CORE_RESET);
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exynos_elb_writel(exynos_pcie, 1, PCIE_STICKY_RESET);
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exynos_elb_writel(exynos_pcie, 1, PCIE_NONSTICKY_RESET);
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exynos_elb_writel(exynos_pcie, 1, PCIE_APP_INIT_RESET);
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exynos_elb_writel(exynos_pcie, 0, PCIE_APP_INIT_RESET);
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exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_MAC_RESET);
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}
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static void exynos_pcie_assert_phy_reset(struct pcie_port *pp)
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{
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struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
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exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_MAC_RESET);
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exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_GLOBAL_RESET);
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}
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static void exynos_pcie_deassert_phy_reset(struct pcie_port *pp)
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{
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struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
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exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_GLOBAL_RESET);
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exynos_elb_writel(exynos_pcie, 1, PCIE_PWR_RESET);
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exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_COMMON_RESET);
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exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_CMN_REG);
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exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_TRSVREG_RESET);
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exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_TRSV_RESET);
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}
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static void exynos_pcie_power_on_phy(struct pcie_port *pp)
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{
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u32 val;
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struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
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val = exynos_phy_readl(exynos_pcie, PCIE_PHY_COMMON_POWER);
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val &= ~PCIE_PHY_COMMON_PD_CMN;
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exynos_phy_writel(exynos_pcie, val, PCIE_PHY_COMMON_POWER);
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val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV0_POWER);
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val &= ~PCIE_PHY_TRSV0_PD_TSV;
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exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV0_POWER);
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val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV1_POWER);
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val &= ~PCIE_PHY_TRSV1_PD_TSV;
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exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV1_POWER);
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val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV2_POWER);
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val &= ~PCIE_PHY_TRSV2_PD_TSV;
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exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV2_POWER);
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val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV3_POWER);
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val &= ~PCIE_PHY_TRSV3_PD_TSV;
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exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV3_POWER);
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}
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static void exynos_pcie_power_off_phy(struct pcie_port *pp)
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{
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u32 val;
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struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
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val = exynos_phy_readl(exynos_pcie, PCIE_PHY_COMMON_POWER);
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val |= PCIE_PHY_COMMON_PD_CMN;
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exynos_phy_writel(exynos_pcie, val, PCIE_PHY_COMMON_POWER);
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val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV0_POWER);
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val |= PCIE_PHY_TRSV0_PD_TSV;
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exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV0_POWER);
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val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV1_POWER);
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val |= PCIE_PHY_TRSV1_PD_TSV;
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exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV1_POWER);
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val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV2_POWER);
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val |= PCIE_PHY_TRSV2_PD_TSV;
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exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV2_POWER);
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val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV3_POWER);
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val |= PCIE_PHY_TRSV3_PD_TSV;
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exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV3_POWER);
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}
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static void exynos_pcie_init_phy(struct pcie_port *pp)
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{
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struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
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/* DCC feedback control off */
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exynos_phy_writel(exynos_pcie, 0x29, PCIE_PHY_DCC_FEEDBACK);
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/* set TX/RX impedance */
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exynos_phy_writel(exynos_pcie, 0xd5, PCIE_PHY_IMPEDANCE);
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/* set 50Mhz PHY clock */
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exynos_phy_writel(exynos_pcie, 0x14, PCIE_PHY_PLL_DIV_0);
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exynos_phy_writel(exynos_pcie, 0x12, PCIE_PHY_PLL_DIV_1);
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/* set TX Differential output for lane 0 */
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exynos_phy_writel(exynos_pcie, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);
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/* set TX Pre-emphasis Level Control for lane 0 to minimum */
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exynos_phy_writel(exynos_pcie, 0x0, PCIE_PHY_TRSV0_EMP_LVL);
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/* set RX clock and data recovery bandwidth */
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exynos_phy_writel(exynos_pcie, 0xe7, PCIE_PHY_PLL_BIAS);
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exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV0_RXCDR);
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exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV1_RXCDR);
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exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV2_RXCDR);
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exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV3_RXCDR);
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/* change TX Pre-emphasis Level Control for lanes */
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exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
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exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
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exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
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exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV3_EMP_LVL);
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/* set LVCC */
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exynos_phy_writel(exynos_pcie, 0x20, PCIE_PHY_TRSV0_LVCC);
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exynos_phy_writel(exynos_pcie, 0xa0, PCIE_PHY_TRSV1_LVCC);
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exynos_phy_writel(exynos_pcie, 0xa0, PCIE_PHY_TRSV2_LVCC);
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exynos_phy_writel(exynos_pcie, 0xa0, PCIE_PHY_TRSV3_LVCC);
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}
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static void exynos_pcie_assert_reset(struct pcie_port *pp)
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{
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struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
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if (exynos_pcie->reset_gpio >= 0)
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devm_gpio_request_one(pp->dev, exynos_pcie->reset_gpio,
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GPIOF_OUT_INIT_HIGH, "RESET");
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return;
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}
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static int exynos_pcie_establish_link(struct pcie_port *pp)
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{
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u32 val;
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int count = 0;
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struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
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if (dw_pcie_link_up(pp)) {
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dev_err(pp->dev, "Link already up\n");
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return 0;
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}
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/* assert reset signals */
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exynos_pcie_assert_core_reset(pp);
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exynos_pcie_assert_phy_reset(pp);
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/* de-assert phy reset */
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exynos_pcie_deassert_phy_reset(pp);
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/* power on phy */
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exynos_pcie_power_on_phy(pp);
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/* initialize phy */
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exynos_pcie_init_phy(pp);
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/* pulse for common reset */
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exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_COMMON_RESET);
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udelay(500);
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exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_COMMON_RESET);
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/* de-assert core reset */
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exynos_pcie_deassert_core_reset(pp);
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/* setup root complex */
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dw_pcie_setup_rc(pp);
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/* assert reset signal */
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exynos_pcie_assert_reset(pp);
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/* assert LTSSM enable */
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exynos_elb_writel(exynos_pcie, PCIE_ELBI_LTSSM_ENABLE,
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PCIE_APP_LTSSM_ENABLE);
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/* check if the link is up or not */
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while (!dw_pcie_link_up(pp)) {
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mdelay(100);
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count++;
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if (count == 10) {
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while (exynos_phy_readl(exynos_pcie,
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PCIE_PHY_PLL_LOCKED) == 0) {
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val = exynos_blk_readl(exynos_pcie,
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PCIE_PHY_PLL_LOCKED);
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dev_info(pp->dev, "PLL Locked: 0x%x\n", val);
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}
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/* power off phy */
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exynos_pcie_power_off_phy(pp);
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dev_err(pp->dev, "PCIe Link Fail\n");
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
dev_info(pp->dev, "Link up\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void exynos_pcie_clear_irq_pulse(struct pcie_port *pp)
|
|
{
|
|
u32 val;
|
|
struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
|
|
|
|
val = exynos_elb_readl(exynos_pcie, PCIE_IRQ_PULSE);
|
|
exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_PULSE);
|
|
return;
|
|
}
|
|
|
|
static void exynos_pcie_enable_irq_pulse(struct pcie_port *pp)
|
|
{
|
|
u32 val;
|
|
struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
|
|
|
|
/* enable INTX interrupt */
|
|
val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT |
|
|
IRQ_INTC_ASSERT | IRQ_INTD_ASSERT,
|
|
exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_EN_PULSE);
|
|
return;
|
|
}
|
|
|
|
static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg)
|
|
{
|
|
struct pcie_port *pp = arg;
|
|
|
|
exynos_pcie_clear_irq_pulse(pp);
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static irqreturn_t exynos_pcie_msi_irq_handler(int irq, void *arg)
|
|
{
|
|
struct pcie_port *pp = arg;
|
|
|
|
return dw_handle_msi_irq(pp);
|
|
}
|
|
|
|
static void exynos_pcie_msi_init(struct pcie_port *pp)
|
|
{
|
|
u32 val;
|
|
struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
|
|
|
|
dw_pcie_msi_init(pp);
|
|
|
|
/* enable MSI interrupt */
|
|
val = exynos_elb_readl(exynos_pcie, PCIE_IRQ_EN_LEVEL);
|
|
val |= IRQ_MSI_ENABLE;
|
|
exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_EN_LEVEL);
|
|
return;
|
|
}
|
|
|
|
static void exynos_pcie_enable_interrupts(struct pcie_port *pp)
|
|
{
|
|
exynos_pcie_enable_irq_pulse(pp);
|
|
|
|
if (IS_ENABLED(CONFIG_PCI_MSI))
|
|
exynos_pcie_msi_init(pp);
|
|
|
|
return;
|
|
}
|
|
|
|
static inline void exynos_pcie_readl_rc(struct pcie_port *pp,
|
|
void __iomem *dbi_base, u32 *val)
|
|
{
|
|
exynos_pcie_sideband_dbi_r_mode(pp, true);
|
|
*val = readl(dbi_base);
|
|
exynos_pcie_sideband_dbi_r_mode(pp, false);
|
|
return;
|
|
}
|
|
|
|
static inline void exynos_pcie_writel_rc(struct pcie_port *pp,
|
|
u32 val, void __iomem *dbi_base)
|
|
{
|
|
exynos_pcie_sideband_dbi_w_mode(pp, true);
|
|
writel(val, dbi_base);
|
|
exynos_pcie_sideband_dbi_w_mode(pp, false);
|
|
return;
|
|
}
|
|
|
|
static int exynos_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
|
|
u32 *val)
|
|
{
|
|
int ret;
|
|
|
|
exynos_pcie_sideband_dbi_r_mode(pp, true);
|
|
ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);
|
|
exynos_pcie_sideband_dbi_r_mode(pp, false);
|
|
return ret;
|
|
}
|
|
|
|
static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
|
|
u32 val)
|
|
{
|
|
int ret;
|
|
|
|
exynos_pcie_sideband_dbi_w_mode(pp, true);
|
|
ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3),
|
|
where, size, val);
|
|
exynos_pcie_sideband_dbi_w_mode(pp, false);
|
|
return ret;
|
|
}
|
|
|
|
static int exynos_pcie_link_up(struct pcie_port *pp)
|
|
{
|
|
struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
|
|
u32 val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_RDLH_LINKUP);
|
|
|
|
if (val == PCIE_ELBI_LTSSM_ENABLE)
|
|
return 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void exynos_pcie_host_init(struct pcie_port *pp)
|
|
{
|
|
exynos_pcie_establish_link(pp);
|
|
exynos_pcie_enable_interrupts(pp);
|
|
}
|
|
|
|
static struct pcie_host_ops exynos_pcie_host_ops = {
|
|
.readl_rc = exynos_pcie_readl_rc,
|
|
.writel_rc = exynos_pcie_writel_rc,
|
|
.rd_own_conf = exynos_pcie_rd_own_conf,
|
|
.wr_own_conf = exynos_pcie_wr_own_conf,
|
|
.link_up = exynos_pcie_link_up,
|
|
.host_init = exynos_pcie_host_init,
|
|
};
|
|
|
|
static int __init add_pcie_port(struct pcie_port *pp,
|
|
struct platform_device *pdev)
|
|
{
|
|
int ret;
|
|
|
|
pp->irq = platform_get_irq(pdev, 1);
|
|
if (!pp->irq) {
|
|
dev_err(&pdev->dev, "failed to get irq\n");
|
|
return -ENODEV;
|
|
}
|
|
ret = devm_request_irq(&pdev->dev, pp->irq, exynos_pcie_irq_handler,
|
|
IRQF_SHARED, "exynos-pcie", pp);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "failed to request irq\n");
|
|
return ret;
|
|
}
|
|
|
|
if (IS_ENABLED(CONFIG_PCI_MSI)) {
|
|
pp->msi_irq = platform_get_irq(pdev, 0);
|
|
if (!pp->msi_irq) {
|
|
dev_err(&pdev->dev, "failed to get msi irq\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
ret = devm_request_irq(&pdev->dev, pp->msi_irq,
|
|
exynos_pcie_msi_irq_handler,
|
|
IRQF_SHARED, "exynos-pcie", pp);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "failed to request msi irq\n");
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
pp->root_bus_nr = -1;
|
|
pp->ops = &exynos_pcie_host_ops;
|
|
|
|
ret = dw_pcie_host_init(pp);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "failed to initialize host\n");
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __init exynos_pcie_probe(struct platform_device *pdev)
|
|
{
|
|
struct exynos_pcie *exynos_pcie;
|
|
struct pcie_port *pp;
|
|
struct device_node *np = pdev->dev.of_node;
|
|
struct resource *elbi_base;
|
|
struct resource *phy_base;
|
|
struct resource *block_base;
|
|
int ret;
|
|
|
|
exynos_pcie = devm_kzalloc(&pdev->dev, sizeof(*exynos_pcie),
|
|
GFP_KERNEL);
|
|
if (!exynos_pcie)
|
|
return -ENOMEM;
|
|
|
|
pp = &exynos_pcie->pp;
|
|
|
|
pp->dev = &pdev->dev;
|
|
|
|
exynos_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
|
|
|
|
exynos_pcie->clk = devm_clk_get(&pdev->dev, "pcie");
|
|
if (IS_ERR(exynos_pcie->clk)) {
|
|
dev_err(&pdev->dev, "Failed to get pcie rc clock\n");
|
|
return PTR_ERR(exynos_pcie->clk);
|
|
}
|
|
ret = clk_prepare_enable(exynos_pcie->clk);
|
|
if (ret)
|
|
return ret;
|
|
|
|
exynos_pcie->bus_clk = devm_clk_get(&pdev->dev, "pcie_bus");
|
|
if (IS_ERR(exynos_pcie->bus_clk)) {
|
|
dev_err(&pdev->dev, "Failed to get pcie bus clock\n");
|
|
ret = PTR_ERR(exynos_pcie->bus_clk);
|
|
goto fail_clk;
|
|
}
|
|
ret = clk_prepare_enable(exynos_pcie->bus_clk);
|
|
if (ret)
|
|
goto fail_clk;
|
|
|
|
elbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
exynos_pcie->elbi_base = devm_ioremap_resource(&pdev->dev, elbi_base);
|
|
if (IS_ERR(exynos_pcie->elbi_base)) {
|
|
ret = PTR_ERR(exynos_pcie->elbi_base);
|
|
goto fail_bus_clk;
|
|
}
|
|
|
|
phy_base = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
|
exynos_pcie->phy_base = devm_ioremap_resource(&pdev->dev, phy_base);
|
|
if (IS_ERR(exynos_pcie->phy_base)) {
|
|
ret = PTR_ERR(exynos_pcie->phy_base);
|
|
goto fail_bus_clk;
|
|
}
|
|
|
|
block_base = platform_get_resource(pdev, IORESOURCE_MEM, 2);
|
|
exynos_pcie->block_base = devm_ioremap_resource(&pdev->dev, block_base);
|
|
if (IS_ERR(exynos_pcie->block_base)) {
|
|
ret = PTR_ERR(exynos_pcie->block_base);
|
|
goto fail_bus_clk;
|
|
}
|
|
|
|
ret = add_pcie_port(pp, pdev);
|
|
if (ret < 0)
|
|
goto fail_bus_clk;
|
|
|
|
platform_set_drvdata(pdev, exynos_pcie);
|
|
return 0;
|
|
|
|
fail_bus_clk:
|
|
clk_disable_unprepare(exynos_pcie->bus_clk);
|
|
fail_clk:
|
|
clk_disable_unprepare(exynos_pcie->clk);
|
|
return ret;
|
|
}
|
|
|
|
static int __exit exynos_pcie_remove(struct platform_device *pdev)
|
|
{
|
|
struct exynos_pcie *exynos_pcie = platform_get_drvdata(pdev);
|
|
|
|
clk_disable_unprepare(exynos_pcie->bus_clk);
|
|
clk_disable_unprepare(exynos_pcie->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id exynos_pcie_of_match[] = {
|
|
{ .compatible = "samsung,exynos5440-pcie", },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, exynos_pcie_of_match);
|
|
|
|
static struct platform_driver exynos_pcie_driver = {
|
|
.remove = __exit_p(exynos_pcie_remove),
|
|
.driver = {
|
|
.name = "exynos-pcie",
|
|
.owner = THIS_MODULE,
|
|
.of_match_table = exynos_pcie_of_match,
|
|
},
|
|
};
|
|
|
|
/* Exynos PCIe driver does not allow module unload */
|
|
|
|
static int __init pcie_init(void)
|
|
{
|
|
return platform_driver_probe(&exynos_pcie_driver, exynos_pcie_probe);
|
|
}
|
|
subsys_initcall(pcie_init);
|
|
|
|
MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
|
|
MODULE_DESCRIPTION("Samsung PCIe host controller driver");
|
|
MODULE_LICENSE("GPL v2");
|