Santosh Shilimkar 247c445c0f ARM: OMAP5: Add the WakeupGen IP updates ... OMAP4 and OMAP5 share same WakeupGen IP with below few udpates on OMAP5. - Additional 32 interrupt support is added w.r.t OMAP4 design. - The AUX CORE boot registers are now made accessible from non-secure SW. - SAR offset are changed and PTMSYNC* registers are removed from SAR. Patch updates the WakeupGen code accordingly. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>		2012-07-09 19:14:39 +05:30
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mach	ARM: OMAP5: Add the WakeupGen IP updates	2012-07-09 19:14:39 +05:30