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a6c19dfe39
The core mm code will provide a default gate area based on FIXADDR_USER_START and FIXADDR_USER_END if !defined(__HAVE_ARCH_GATE_AREA) && defined(AT_SYSINFO_EHDR). This default is only useful for ia64. arm64, ppc, s390, sh, tile, 64-bit UML, and x86_32 have their own code just to disable it. arm, 32-bit UML, and x86_64 have gate areas, but they have their own implementations. This gets rid of the default and moves the code into ia64. This should save some code on architectures without a gate area: it's now possible to inline the gate_area functions in the default case. Signed-off-by: Andy Lutomirski <luto@amacapital.net> Acked-by: Nathan Lynch <nathan_lynch@mentor.com> Acked-by: H. Peter Anvin <hpa@linux.intel.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [in principle] Acked-by: Richard Weinberger <richard@nod.at> [for um] Acked-by: Will Deacon <will.deacon@arm.com> [for arm64] Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Tony Luck <tony.luck@intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: Chris Metcalf <cmetcalf@tilera.com> Cc: Jeff Dike <jdike@addtoit.com> Cc: Richard Weinberger <richard@nod.at> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Nathan Lynch <Nathan_Lynch@mentor.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
166 lines
4.5 KiB
C
166 lines
4.5 KiB
C
/*
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* S390 version
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* Copyright IBM Corp. 1999, 2000
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* Author(s): Hartmut Penner (hp@de.ibm.com)
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*/
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#ifndef _S390_PAGE_H
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#define _S390_PAGE_H
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#include <linux/const.h>
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#include <asm/types.h>
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/* PAGE_SHIFT determines the page size */
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#define PAGE_SHIFT 12
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#define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT)
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#define PAGE_MASK (~(PAGE_SIZE-1))
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#define PAGE_DEFAULT_ACC 0
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#define PAGE_DEFAULT_KEY (PAGE_DEFAULT_ACC << 4)
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#define HPAGE_SHIFT 20
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#define HPAGE_SIZE (1UL << HPAGE_SHIFT)
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#define HPAGE_MASK (~(HPAGE_SIZE - 1))
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#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
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#define ARCH_HAS_SETCLEAR_HUGE_PTE
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#define ARCH_HAS_HUGE_PTE_TYPE
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#define ARCH_HAS_PREPARE_HUGEPAGE
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#define ARCH_HAS_HUGEPAGE_CLEAR_FLUSH
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#include <asm/setup.h>
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#ifndef __ASSEMBLY__
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static inline void storage_key_init_range(unsigned long start, unsigned long end)
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{
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#if PAGE_DEFAULT_KEY
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__storage_key_init_range(start, end);
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#endif
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}
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static inline void clear_page(void *page)
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{
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register unsigned long reg1 asm ("1") = 0;
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register void *reg2 asm ("2") = page;
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register unsigned long reg3 asm ("3") = 4096;
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asm volatile(
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" mvcl 2,0"
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: "+d" (reg2), "+d" (reg3) : "d" (reg1)
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: "memory", "cc");
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}
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/*
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* copy_page uses the mvcl instruction with 0xb0 padding byte in order to
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* bypass caches when copying a page. Especially when copying huge pages
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* this keeps L1 and L2 data caches alive.
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*/
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static inline void copy_page(void *to, void *from)
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{
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register void *reg2 asm ("2") = to;
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register unsigned long reg3 asm ("3") = 0x1000;
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register void *reg4 asm ("4") = from;
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register unsigned long reg5 asm ("5") = 0xb0001000;
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asm volatile(
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" mvcl 2,4"
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: "+d" (reg2), "+d" (reg3), "+d" (reg4), "+d" (reg5)
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: : "memory", "cc");
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}
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#define clear_user_page(page, vaddr, pg) clear_page(page)
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#define copy_user_page(to, from, vaddr, pg) copy_page(to, from)
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#define __alloc_zeroed_user_highpage(movableflags, vma, vaddr) \
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alloc_page_vma(GFP_HIGHUSER | __GFP_ZERO | movableflags, vma, vaddr)
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#define __HAVE_ARCH_ALLOC_ZEROED_USER_HIGHPAGE
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/*
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* These are used to make use of C type-checking..
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*/
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typedef struct { unsigned long pgprot; } pgprot_t;
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typedef struct { unsigned long pgste; } pgste_t;
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typedef struct { unsigned long pte; } pte_t;
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typedef struct { unsigned long pmd; } pmd_t;
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typedef struct { unsigned long pud; } pud_t;
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typedef struct { unsigned long pgd; } pgd_t;
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typedef pte_t *pgtable_t;
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#define pgprot_val(x) ((x).pgprot)
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#define pgste_val(x) ((x).pgste)
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#define pte_val(x) ((x).pte)
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#define pmd_val(x) ((x).pmd)
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#define pud_val(x) ((x).pud)
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#define pgd_val(x) ((x).pgd)
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#define __pgste(x) ((pgste_t) { (x) } )
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#define __pte(x) ((pte_t) { (x) } )
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#define __pmd(x) ((pmd_t) { (x) } )
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#define __pud(x) ((pud_t) { (x) } )
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#define __pgd(x) ((pgd_t) { (x) } )
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#define __pgprot(x) ((pgprot_t) { (x) } )
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static inline void page_set_storage_key(unsigned long addr,
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unsigned char skey, int mapped)
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{
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if (!mapped)
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asm volatile(".insn rrf,0xb22b0000,%0,%1,8,0"
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: : "d" (skey), "a" (addr));
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else
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asm volatile("sske %0,%1" : : "d" (skey), "a" (addr));
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}
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static inline unsigned char page_get_storage_key(unsigned long addr)
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{
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unsigned char skey;
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asm volatile("iske %0,%1" : "=d" (skey) : "a" (addr));
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return skey;
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}
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static inline int page_reset_referenced(unsigned long addr)
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{
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unsigned int ipm;
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asm volatile(
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" rrbe 0,%1\n"
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" ipm %0\n"
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: "=d" (ipm) : "a" (addr) : "cc");
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return !!(ipm & 0x20000000);
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}
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/* Bits int the storage key */
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#define _PAGE_CHANGED 0x02 /* HW changed bit */
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#define _PAGE_REFERENCED 0x04 /* HW referenced bit */
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#define _PAGE_FP_BIT 0x08 /* HW fetch protection bit */
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#define _PAGE_ACC_BITS 0xf0 /* HW access control bits */
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struct page;
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void arch_free_page(struct page *page, int order);
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void arch_alloc_page(struct page *page, int order);
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void arch_set_page_states(int make_stable);
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static inline int devmem_is_allowed(unsigned long pfn)
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{
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return 0;
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}
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#define HAVE_ARCH_FREE_PAGE
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#define HAVE_ARCH_ALLOC_PAGE
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#endif /* !__ASSEMBLY__ */
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#define __PAGE_OFFSET 0x0UL
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#define PAGE_OFFSET 0x0UL
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#define __pa(x) (unsigned long)(x)
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#define __va(x) (void *)(unsigned long)(x)
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#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
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#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
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#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
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#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | \
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VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
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#include <asm-generic/memory_model.h>
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#include <asm-generic/getorder.h>
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#endif /* _S390_PAGE_H */
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