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5c8d08f347
Add definitions for the Tegra20+ memory controller hot resets. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
58 lines
1.7 KiB
C
58 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef DT_BINDINGS_MEMORY_TEGRA124_MC_H
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#define DT_BINDINGS_MEMORY_TEGRA124_MC_H
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#define TEGRA_SWGROUP_PTC 0
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#define TEGRA_SWGROUP_DC 1
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#define TEGRA_SWGROUP_DCB 2
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#define TEGRA_SWGROUP_AFI 3
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#define TEGRA_SWGROUP_AVPC 4
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#define TEGRA_SWGROUP_HDA 5
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#define TEGRA_SWGROUP_HC 6
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#define TEGRA_SWGROUP_MSENC 7
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#define TEGRA_SWGROUP_PPCS 8
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#define TEGRA_SWGROUP_SATA 9
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#define TEGRA_SWGROUP_VDE 10
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#define TEGRA_SWGROUP_MPCORELP 11
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#define TEGRA_SWGROUP_MPCORE 12
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#define TEGRA_SWGROUP_ISP2 13
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#define TEGRA_SWGROUP_XUSB_HOST 14
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#define TEGRA_SWGROUP_XUSB_DEV 15
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#define TEGRA_SWGROUP_ISP2B 16
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#define TEGRA_SWGROUP_TSEC 17
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#define TEGRA_SWGROUP_A9AVP 18
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#define TEGRA_SWGROUP_GPU 19
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#define TEGRA_SWGROUP_SDMMC1A 20
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#define TEGRA_SWGROUP_SDMMC2A 21
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#define TEGRA_SWGROUP_SDMMC3A 22
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#define TEGRA_SWGROUP_SDMMC4A 23
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#define TEGRA_SWGROUP_VIC 24
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#define TEGRA_SWGROUP_VI 25
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#define TEGRA124_MC_RESET_AFI 0
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#define TEGRA124_MC_RESET_AVPC 1
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#define TEGRA124_MC_RESET_DC 2
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#define TEGRA124_MC_RESET_DCB 3
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#define TEGRA124_MC_RESET_HC 4
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#define TEGRA124_MC_RESET_HDA 5
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#define TEGRA124_MC_RESET_ISP2 6
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#define TEGRA124_MC_RESET_MPCORE 7
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#define TEGRA124_MC_RESET_MPCORELP 8
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#define TEGRA124_MC_RESET_MSENC 9
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#define TEGRA124_MC_RESET_PPCS 10
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#define TEGRA124_MC_RESET_SATA 11
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#define TEGRA124_MC_RESET_VDE 12
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#define TEGRA124_MC_RESET_VI 13
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#define TEGRA124_MC_RESET_VIC 14
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#define TEGRA124_MC_RESET_XUSB_HOST 15
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#define TEGRA124_MC_RESET_XUSB_DEV 16
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#define TEGRA124_MC_RESET_TSEC 17
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#define TEGRA124_MC_RESET_SDMMC1 18
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#define TEGRA124_MC_RESET_SDMMC2 19
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#define TEGRA124_MC_RESET_SDMMC3 20
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#define TEGRA124_MC_RESET_SDMMC4 21
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#define TEGRA124_MC_RESET_ISP2B 22
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#define TEGRA124_MC_RESET_GPU 23
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#endif
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