Serge Semin 2313fca7b4 dt-bindings: memory: Add Baikal-T1 L2-cache Control Block binding ... There is a single register provided by the SoC system controller, which can be used to tune the L2-cache RAM up. It only provides a way to change the L2-RAM access latencies. So aside from "be,bt1-l2-ctl" compatible string the device node can be optionally equipped with the properties of Tag/Data/WS latencies. Link: https://lore.kernel.org/r/20200526125928.17096-4-Sergey.Semin@baikalelectronics.ru Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> Cc: Paul Burton <paulburton@kernel.org> Cc: Olof Johansson <olof@lixom.net> Cc: linux-mips@vger.kernel.org Cc: soc@kernel.org Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>		2020-05-28 16:56:12 +02:00
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bindings	dt-bindings: memory: Add Baikal-T1 L2-cache Control Block binding	2020-05-28 16:56:12 +02:00
booting-without-of.txt
changesets.txt
dynamic-resolution-notes.txt
of_unittest.txt
overlay-notes.txt
usage-model.txt
writing-schema.rst	kbuild: allow to run dt_binding_check and dtbs_check in a single command	2020-03-13 10:04:36 +09:00