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58b71c3ec7
The iomux function declarations are in headers only accessible in this directory. Thus those can't be used in any module. None of the objects in this directory is tristate. Neither can the header be included in out-of-tree modules. Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
175 lines
4.1 KiB
C
175 lines
4.1 KiB
C
/*
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* Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
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* Copyright (C) 2009 by Valentin Longchamp <valentin.longchamp@epfl.ch>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#include <linux/gpio.h>
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#include <linux/module.h>
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include "hardware.h"
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#include "iomux-mx3.h"
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/*
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* IOMUX register (base) addresses
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*/
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#define IOMUX_BASE MX31_IO_ADDRESS(MX31_IOMUXC_BASE_ADDR)
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#define IOMUXINT_OBS1 (IOMUX_BASE + 0x000)
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#define IOMUXINT_OBS2 (IOMUX_BASE + 0x004)
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#define IOMUXGPR (IOMUX_BASE + 0x008)
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#define IOMUXSW_MUX_CTL (IOMUX_BASE + 0x00C)
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#define IOMUXSW_PAD_CTL (IOMUX_BASE + 0x154)
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static DEFINE_SPINLOCK(gpio_mux_lock);
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#define IOMUX_REG_MASK (IOMUX_PADNUM_MASK & ~0x3)
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static unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG];
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/*
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* set the mode for a IOMUX pin.
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*/
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int mxc_iomux_mode(unsigned int pin_mode)
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{
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u32 field, l, mode, ret = 0;
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void __iomem *reg;
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reg = IOMUXSW_MUX_CTL + (pin_mode & IOMUX_REG_MASK);
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field = pin_mode & 0x3;
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mode = (pin_mode & IOMUX_MODE_MASK) >> IOMUX_MODE_SHIFT;
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spin_lock(&gpio_mux_lock);
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l = __raw_readl(reg);
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l &= ~(0xff << (field * 8));
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l |= mode << (field * 8);
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__raw_writel(l, reg);
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spin_unlock(&gpio_mux_lock);
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return ret;
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}
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/*
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* This function configures the pad value for a IOMUX pin.
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*/
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void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
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{
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u32 field, l;
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void __iomem *reg;
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pin &= IOMUX_PADNUM_MASK;
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reg = IOMUXSW_PAD_CTL + (pin + 2) / 3 * 4;
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field = (pin + 2) % 3;
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pr_debug("%s: reg offset = 0x%x, field = %d\n",
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__func__, (pin + 2) / 3, field);
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spin_lock(&gpio_mux_lock);
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l = __raw_readl(reg);
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l &= ~(0x1ff << (field * 10));
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l |= config << (field * 10);
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__raw_writel(l, reg);
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spin_unlock(&gpio_mux_lock);
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}
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/*
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* allocs a single pin:
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* - reserves the pin so that it is not claimed by another driver
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* - setups the iomux according to the configuration
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*/
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int mxc_iomux_alloc_pin(unsigned int pin, const char *label)
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{
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unsigned pad = pin & IOMUX_PADNUM_MASK;
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if (pad >= (PIN_MAX + 1)) {
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printk(KERN_ERR "mxc_iomux: Attempt to request nonexistant pin %u for \"%s\"\n",
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pad, label ? label : "?");
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return -EINVAL;
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}
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if (test_and_set_bit(pad, mxc_pin_alloc_map)) {
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printk(KERN_ERR "mxc_iomux: pin %u already used. Allocation for \"%s\" failed\n",
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pad, label ? label : "?");
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return -EBUSY;
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}
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mxc_iomux_mode(pin);
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return 0;
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}
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int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
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const char *label)
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{
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const unsigned int *p = pin_list;
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int i;
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int ret = -EINVAL;
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for (i = 0; i < count; i++) {
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ret = mxc_iomux_alloc_pin(*p, label);
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if (ret)
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goto setup_error;
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p++;
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}
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return 0;
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setup_error:
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mxc_iomux_release_multiple_pins(pin_list, i);
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return ret;
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}
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void mxc_iomux_release_pin(unsigned int pin)
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{
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unsigned pad = pin & IOMUX_PADNUM_MASK;
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if (pad < (PIN_MAX + 1))
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clear_bit(pad, mxc_pin_alloc_map);
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}
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void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count)
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{
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const unsigned int *p = pin_list;
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int i;
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for (i = 0; i < count; i++) {
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mxc_iomux_release_pin(*p);
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p++;
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}
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}
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/*
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* This function enables/disables the general purpose function for a particular
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* signal.
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*/
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void mxc_iomux_set_gpr(enum iomux_gp_func gp, bool en)
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{
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u32 l;
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spin_lock(&gpio_mux_lock);
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l = __raw_readl(IOMUXGPR);
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if (en)
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l |= gp;
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else
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l &= ~gp;
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__raw_writel(l, IOMUXGPR);
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spin_unlock(&gpio_mux_lock);
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}
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