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592a607bbc
It appears that with the U3 northbridge, if the processor is in NAP mode the whole time while waiting for an SMU command to complete, then the SMU will fail. It could be related to the weird backward mechanism the SMU uses to get to system memory via i2c to the northbridge that doesn't operate properly when the said bridge is in napping along with the CPU. That is on U3 at least, U4 doesn't seem to be affected. This didn't show before NO_HZ as the timer wakeup was enough to make it work it seems, but that is no longer the case. This fixes it by disabling NAP mode on those machines while an SMU command is in flight. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org> |
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| .. | ||
| backlight.c | ||
| bootx_init.c | ||
| cache.S | ||
| cpufreq_32.c | ||
| cpufreq_64.c | ||
| feature.c | ||
| Kconfig | ||
| low_i2c.c | ||
| Makefile | ||
| nvram.c | ||
| pci.c | ||
| pfunc_base.c | ||
| pfunc_core.c | ||
| pic.c | ||
| pic.h | ||
| pmac.h | ||
| setup.c | ||
| sleep.S | ||
| smp.c | ||
| time.c | ||
| udbg_adb.c | ||
| udbg_scc.c | ||