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86853c83e3
Add gpio offset into "gpio-range-cells" property. It's used to support sparse pinctrl range in gpio chip. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
119 lines
2.9 KiB
Plaintext
119 lines
2.9 KiB
Plaintext
/*
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* DTS file for SPEAr310 SoC
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*
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* Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/include/ "spear3xx.dtsi"
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/ {
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ahb {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0x40000000 0x40000000 0x10000000
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0xb0000000 0xb0000000 0x10000000
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0xd0000000 0xd0000000 0x30000000>;
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pinmux: pinmux@b4000000 {
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compatible = "st,spear310-pinmux";
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reg = <0xb4000000 0x1000>;
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#gpio-range-cells = <3>;
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};
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fsmc: flash@44000000 {
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compatible = "st,spear600-fsmc-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x44000000 0x1000 /* FSMC Register */
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0x40000000 0x0010 /* NAND Base DATA */
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0x40020000 0x0010 /* NAND Base ADDR */
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0x40010000 0x0010>; /* NAND Base CMD */
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reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
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status = "disabled";
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};
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shirq: interrupt-controller@0xb4000000 {
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compatible = "st,spear310-shirq";
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reg = <0xb4000000 0x1000>;
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interrupts = <28 29 30 1>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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apb {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0xb0000000 0xb0000000 0x10000000
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0xd0000000 0xd0000000 0x30000000>;
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serial@b2000000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0xb2000000 0x1000>;
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interrupts = <8>;
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interrupt-parent = <&shirq>;
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status = "disabled";
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};
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serial@b2080000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0xb2080000 0x1000>;
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interrupts = <9>;
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interrupt-parent = <&shirq>;
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status = "disabled";
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};
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serial@b2100000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0xb2100000 0x1000>;
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interrupts = <10>;
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interrupt-parent = <&shirq>;
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status = "disabled";
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};
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serial@b2180000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0xb2180000 0x1000>;
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interrupts = <11>;
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interrupt-parent = <&shirq>;
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status = "disabled";
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};
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serial@b2200000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0xb2200000 0x1000>;
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interrupts = <12>;
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interrupt-parent = <&shirq>;
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status = "disabled";
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};
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gpiopinctrl: gpio@b4000000 {
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compatible = "st,spear-plgpio";
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reg = <0xb4000000 0x1000>;
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#interrupt-cells = <1>;
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interrupt-controller;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinmux 0 0 102>;
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status = "disabled";
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st-plgpio,ngpio = <102>;
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st-plgpio,enb-reg = <0x10>;
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st-plgpio,wdata-reg = <0x20>;
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st-plgpio,dir-reg = <0x30>;
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st-plgpio,ie-reg = <0x50>;
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st-plgpio,rdata-reg = <0x40>;
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st-plgpio,mis-reg = <0x60>;
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};
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};
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};
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};
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