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4b98d9e713
Not all 64-bit Book-3E parts will have fixed IVORs so add a function that cpusetup code can call to setup the base IVORs (0..15) to match the fixed offsets. We need to 'or' part of interrupt_base_book3e into the IVORs since on parts that have them the IVPR doesn't extend as far down. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
206 lines
6.9 KiB
C
206 lines
6.9 KiB
C
/*
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* Definitions for use by exception code on Book3-E
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*
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* Copyright (C) 2008 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _ASM_POWERPC_EXCEPTION_64E_H
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#define _ASM_POWERPC_EXCEPTION_64E_H
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/*
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* SPRGs usage an other considerations...
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*
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* Since TLB miss and other standard exceptions can be interrupted by
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* critical exceptions which can themselves be interrupted by machine
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* checks, and since the two later can themselves cause a TLB miss when
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* hitting the linear mapping for the kernel stacks, we need to be a bit
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* creative on how we use SPRGs.
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*
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* The base idea is that we have one SRPG reserved for critical and one
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* for machine check interrupts. Those are used to save a GPR that can
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* then be used to get the PACA, and store as much context as we need
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* to save in there. That includes saving the SPRGs used by the TLB miss
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* handler for linear mapping misses and the associated SRR0/1 due to
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* the above re-entrancy issue.
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*
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* So here's the current usage pattern. It's done regardless of which
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* SPRGs are user-readable though, thus we might have to change some of
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* this later. In order to do that more easily, we use special constants
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* for naming them
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*
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* WARNING: Some of these SPRGs are user readable. We need to do something
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* about it as some point by making sure they can't be used to leak kernel
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* critical data
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*/
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/* We are out of SPRGs so we save some things in the PACA. The normal
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* exception frame is smaller than the CRIT or MC one though
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*/
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#define EX_R1 (0 * 8)
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#define EX_CR (1 * 8)
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#define EX_R10 (2 * 8)
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#define EX_R11 (3 * 8)
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#define EX_R14 (4 * 8)
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#define EX_R15 (5 * 8)
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/* The TLB miss exception uses different slots */
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#define EX_TLB_R10 ( 0 * 8)
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#define EX_TLB_R11 ( 1 * 8)
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#define EX_TLB_R12 ( 2 * 8)
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#define EX_TLB_R13 ( 3 * 8)
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#define EX_TLB_R14 ( 4 * 8)
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#define EX_TLB_R15 ( 5 * 8)
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#define EX_TLB_R16 ( 6 * 8)
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#define EX_TLB_CR ( 7 * 8)
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#define EX_TLB_DEAR ( 8 * 8) /* Level 0 and 2 only */
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#define EX_TLB_ESR ( 9 * 8) /* Level 0 and 2 only */
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#define EX_TLB_SRR0 (10 * 8)
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#define EX_TLB_SRR1 (11 * 8)
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#define EX_TLB_MMUCR0 (12 * 8) /* Level 0 */
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#define EX_TLB_MAS1 (12 * 8) /* Level 0 */
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#define EX_TLB_MAS2 (13 * 8) /* Level 0 */
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#ifdef CONFIG_BOOK3E_MMU_TLB_STATS
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#define EX_TLB_R8 (14 * 8)
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#define EX_TLB_R9 (15 * 8)
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#define EX_TLB_LR (16 * 8)
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#define EX_TLB_SIZE (17 * 8)
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#else
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#define EX_TLB_SIZE (14 * 8)
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#endif
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#define START_EXCEPTION(label) \
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.globl exc_##label##_book3e; \
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exc_##label##_book3e:
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/* TLB miss exception prolog
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*
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* This prolog handles re-entrancy (up to 3 levels supported in the PACA
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* though we currently don't test for overflow). It provides you with a
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* re-entrancy safe working space of r10...r16 and CR with r12 being used
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* as the exception area pointer in the PACA for that level of re-entrancy
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* and r13 containing the PACA pointer.
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*
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* SRR0 and SRR1 are saved, but DEAR and ESR are not, since they don't apply
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* as-is for instruction exceptions. It's up to the actual exception code
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* to save them as well if required.
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*/
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#define TLB_MISS_PROLOG \
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mtspr SPRN_SPRG_TLB_SCRATCH,r12; \
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mfspr r12,SPRN_SPRG_TLB_EXFRAME; \
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std r10,EX_TLB_R10(r12); \
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mfcr r10; \
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std r11,EX_TLB_R11(r12); \
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mfspr r11,SPRN_SPRG_TLB_SCRATCH; \
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std r13,EX_TLB_R13(r12); \
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mfspr r13,SPRN_SPRG_PACA; \
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std r14,EX_TLB_R14(r12); \
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addi r14,r12,EX_TLB_SIZE; \
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std r15,EX_TLB_R15(r12); \
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mfspr r15,SPRN_SRR1; \
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std r16,EX_TLB_R16(r12); \
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mfspr r16,SPRN_SRR0; \
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std r10,EX_TLB_CR(r12); \
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std r11,EX_TLB_R12(r12); \
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mtspr SPRN_SPRG_TLB_EXFRAME,r14; \
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std r15,EX_TLB_SRR1(r12); \
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std r16,EX_TLB_SRR0(r12); \
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TLB_MISS_PROLOG_STATS
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/* And these are the matching epilogs that restores things
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*
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* There are 3 epilogs:
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*
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* - SUCCESS : Unwinds one level
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* - ERROR : restore from level 0 and reset
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* - ERROR_SPECIAL : restore from current level and reset
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*
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* Normal errors use ERROR, that is, they restore the initial fault context
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* and trigger a fault. However, there is a special case for linear mapping
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* errors. Those should basically never happen, but if they do happen, we
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* want the error to point out the context that did that linear mapping
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* fault, not the initial level 0 (basically, we got a bogus PGF or something
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* like that). For userland errors on the linear mapping, there is no
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* difference since those are always level 0 anyway
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*/
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#define TLB_MISS_RESTORE(freg) \
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ld r14,EX_TLB_CR(r12); \
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ld r10,EX_TLB_R10(r12); \
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ld r15,EX_TLB_SRR0(r12); \
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ld r16,EX_TLB_SRR1(r12); \
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mtspr SPRN_SPRG_TLB_EXFRAME,freg; \
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ld r11,EX_TLB_R11(r12); \
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mtcr r14; \
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ld r13,EX_TLB_R13(r12); \
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ld r14,EX_TLB_R14(r12); \
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mtspr SPRN_SRR0,r15; \
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ld r15,EX_TLB_R15(r12); \
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mtspr SPRN_SRR1,r16; \
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TLB_MISS_RESTORE_STATS \
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ld r16,EX_TLB_R16(r12); \
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ld r12,EX_TLB_R12(r12); \
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#define TLB_MISS_EPILOG_SUCCESS \
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TLB_MISS_RESTORE(r12)
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#define TLB_MISS_EPILOG_ERROR \
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addi r12,r13,PACA_EXTLB; \
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TLB_MISS_RESTORE(r12)
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#define TLB_MISS_EPILOG_ERROR_SPECIAL \
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addi r11,r13,PACA_EXTLB; \
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TLB_MISS_RESTORE(r11)
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#ifdef CONFIG_BOOK3E_MMU_TLB_STATS
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#define TLB_MISS_PROLOG_STATS \
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mflr r10; \
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std r8,EX_TLB_R8(r12); \
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std r9,EX_TLB_R9(r12); \
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std r10,EX_TLB_LR(r12);
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#define TLB_MISS_RESTORE_STATS \
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ld r16,EX_TLB_LR(r12); \
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ld r9,EX_TLB_R9(r12); \
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ld r8,EX_TLB_R8(r12); \
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mtlr r16;
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#define TLB_MISS_STATS_D(name) \
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addi r9,r13,MMSTAT_DSTATS+name; \
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bl .tlb_stat_inc;
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#define TLB_MISS_STATS_I(name) \
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addi r9,r13,MMSTAT_ISTATS+name; \
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bl .tlb_stat_inc;
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#define TLB_MISS_STATS_X(name) \
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ld r8,PACA_EXTLB+EX_TLB_ESR(r13); \
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cmpdi cr2,r8,-1; \
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beq cr2,61f; \
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addi r9,r13,MMSTAT_DSTATS+name; \
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b 62f; \
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61: addi r9,r13,MMSTAT_ISTATS+name; \
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62: bl .tlb_stat_inc;
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#define TLB_MISS_STATS_SAVE_INFO \
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std r14,EX_TLB_ESR(r12); /* save ESR */ \
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#else
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#define TLB_MISS_PROLOG_STATS
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#define TLB_MISS_RESTORE_STATS
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#define TLB_MISS_STATS_D(name)
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#define TLB_MISS_STATS_I(name)
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#define TLB_MISS_STATS_X(name)
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#define TLB_MISS_STATS_Y(name)
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#define TLB_MISS_STATS_SAVE_INFO
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#endif
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#define SET_IVOR(vector_number, vector_offset) \
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li r3,vector_offset@l; \
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ori r3,r3,interrupt_base_book3e@l; \
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mtspr SPRN_IVOR##vector_number,r3;
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#endif /* _ASM_POWERPC_EXCEPTION_64E_H */
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