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e4178c7504
- fix noMMU build on cores with MMU. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJYk4VkAAoJEFH5zJH4P6BEdxUP/RQRkWmkoJCf5UI7MQOiU1LS HuT9U4trDyUUPGRYi1oUgSZMjM2IqZZvmUqSQOq7i2Uo52UffTWMBCrniye+CPk9 XLEiAoiD5JCObuDKYQTtpG5BQUqpGsCdV1ZGtpcJofZIef8sxOVvBuyzD+Tr4ok+ OvA4/X20nEX3fp4R2EyEMZg9re+GeJ8vgY/71jAH3bw4SwJ6znsRgNDM2hP7ZaYq yZfqcwpqzfj8Jrx6Nfq9ibM37iVEam3OoIGJbYFpvF+uLsOyRPMABc7d6oJk2cTo hFKfu9TlH7vNZOhh812KLqcJSeLf4TxNAUZqKLrCsZ860QnCZoI63911FxwZX3sU gXYzu4K+c+GhtB48w5UlRlKlHRTqu55MOC+5Pk/lYpm7DXXmgS0cjfRpBvYDFVfH QIcZ6isGht0TKbLcE79nxnLf1miVajQtSYhtVjND93TwB7ryURLlMdriI7nSYF2M RksL8m9di1fsZyIHQTaBOlNc9taxnxWJr+2oSJAzJ7f9QSYC4FdYTRwDujx4mPoe u3w6ED466zPLZzuZeg5qZbZp4s4DGkh9IKHCwZfadmCVtneMlDRV3JRnPvhE740M +syyJMR8HtLfRMto7fkrkUcK7+pV2jTRTwKk06QIoRlTIwR4uKjO6kVdizNwXQPD AqmAMqT0YBntVmDgM6sR =qIDo -----END PGP SIGNATURE----- Merge tag 'xtensa-20170202' of git://github.com/jcmvbkbc/linux-xtensa Pull Xtensa fix from Max Filippov: "A for an Xtensa build error introduced in reset code refactoring series in v4.9: - fix noMMU build on cores with MMU" * tag 'xtensa-20170202' of git://github.com/jcmvbkbc/linux-xtensa: xtensa: fix noMMU build on cores with MMU
728 lines
16 KiB
C
728 lines
16 KiB
C
/*
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* arch/xtensa/kernel/setup.c
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1995 Linus Torvalds
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* Copyright (C) 2001 - 2005 Tensilica Inc.
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* Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
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*
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* Chris Zankel <chris@zankel.net>
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* Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
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* Kevin Chea
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* Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
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*/
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <linux/proc_fs.h>
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#include <linux/screen_info.h>
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#include <linux/bootmem.h>
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#include <linux/kernel.h>
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#include <linux/percpu.h>
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#include <linux/cpu.h>
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#include <linux/of.h>
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#include <linux/of_fdt.h>
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#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
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# include <linux/console.h>
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#endif
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#ifdef CONFIG_PROC_FS
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# include <linux/seq_file.h>
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#endif
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#include <asm/bootparam.h>
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#include <asm/mmu_context.h>
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#include <asm/pgtable.h>
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#include <asm/processor.h>
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#include <asm/timex.h>
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#include <asm/platform.h>
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#include <asm/page.h>
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#include <asm/setup.h>
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#include <asm/param.h>
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#include <asm/smp.h>
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#include <asm/sysmem.h>
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#include <platform/hardware.h>
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#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
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struct screen_info screen_info = {
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.orig_x = 0,
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.orig_y = 24,
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.orig_video_cols = 80,
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.orig_video_lines = 24,
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.orig_video_isVGA = 1,
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.orig_video_points = 16,
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};
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#endif
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#ifdef CONFIG_BLK_DEV_INITRD
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extern unsigned long initrd_start;
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extern unsigned long initrd_end;
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int initrd_is_mapped = 0;
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extern int initrd_below_start_ok;
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#endif
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#ifdef CONFIG_OF
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void *dtb_start = __dtb_start;
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#endif
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extern unsigned long loops_per_jiffy;
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/* Command line specified as configuration option. */
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static char __initdata command_line[COMMAND_LINE_SIZE];
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#ifdef CONFIG_CMDLINE_BOOL
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static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
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#endif
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/*
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* Boot parameter parsing.
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*
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* The Xtensa port uses a list of variable-sized tags to pass data to
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* the kernel. The first tag must be a BP_TAG_FIRST tag for the list
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* to be recognised. The list is terminated with a zero-sized
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* BP_TAG_LAST tag.
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*/
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typedef struct tagtable {
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u32 tag;
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int (*parse)(const bp_tag_t*);
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} tagtable_t;
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#define __tagtable(tag, fn) static tagtable_t __tagtable_##fn \
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__attribute__((used, section(".taglist"))) = { tag, fn }
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/* parse current tag */
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static int __init parse_tag_mem(const bp_tag_t *tag)
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{
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struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
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if (mi->type != MEMORY_TYPE_CONVENTIONAL)
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return -1;
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return memblock_add(mi->start, mi->end - mi->start);
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}
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__tagtable(BP_TAG_MEMORY, parse_tag_mem);
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#ifdef CONFIG_BLK_DEV_INITRD
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static int __init parse_tag_initrd(const bp_tag_t* tag)
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{
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struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
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initrd_start = (unsigned long)__va(mi->start);
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initrd_end = (unsigned long)__va(mi->end);
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return 0;
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}
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__tagtable(BP_TAG_INITRD, parse_tag_initrd);
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#ifdef CONFIG_OF
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static int __init parse_tag_fdt(const bp_tag_t *tag)
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{
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dtb_start = __va(tag->data[0]);
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return 0;
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}
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__tagtable(BP_TAG_FDT, parse_tag_fdt);
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#endif /* CONFIG_OF */
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#endif /* CONFIG_BLK_DEV_INITRD */
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static int __init parse_tag_cmdline(const bp_tag_t* tag)
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{
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strlcpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE);
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return 0;
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}
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__tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline);
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static int __init parse_bootparam(const bp_tag_t* tag)
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{
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extern tagtable_t __tagtable_begin, __tagtable_end;
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tagtable_t *t;
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/* Boot parameters must start with a BP_TAG_FIRST tag. */
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if (tag->id != BP_TAG_FIRST) {
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printk(KERN_WARNING "Invalid boot parameters!\n");
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return 0;
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}
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tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size);
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/* Parse all tags. */
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while (tag != NULL && tag->id != BP_TAG_LAST) {
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for (t = &__tagtable_begin; t < &__tagtable_end; t++) {
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if (tag->id == t->tag) {
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t->parse(tag);
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break;
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}
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}
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if (t == &__tagtable_end)
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printk(KERN_WARNING "Ignoring tag "
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"0x%08x\n", tag->id);
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tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size);
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}
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return 0;
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}
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#ifdef CONFIG_OF
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#if !XCHAL_HAVE_PTP_MMU || XCHAL_HAVE_SPANNING_WAY
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unsigned long xtensa_kio_paddr = XCHAL_KIO_DEFAULT_PADDR;
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EXPORT_SYMBOL(xtensa_kio_paddr);
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static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
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int depth, void *data)
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{
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const __be32 *ranges;
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int len;
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if (depth > 1)
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return 0;
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if (!of_flat_dt_is_compatible(node, "simple-bus"))
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return 0;
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ranges = of_get_flat_dt_prop(node, "ranges", &len);
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if (!ranges)
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return 1;
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if (len == 0)
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return 1;
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xtensa_kio_paddr = of_read_ulong(ranges+1, 1);
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/* round down to nearest 256MB boundary */
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xtensa_kio_paddr &= 0xf0000000;
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return 1;
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}
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#else
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static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
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int depth, void *data)
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{
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return 1;
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}
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#endif
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void __init early_init_dt_add_memory_arch(u64 base, u64 size)
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{
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size &= PAGE_MASK;
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memblock_add(base, size);
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}
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void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
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{
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return __alloc_bootmem(size, align, 0);
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}
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void __init early_init_devtree(void *params)
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{
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early_init_dt_scan(params);
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of_scan_flat_dt(xtensa_dt_io_area, NULL);
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if (!command_line[0])
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strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
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}
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#endif /* CONFIG_OF */
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/*
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* Initialize architecture. (Early stage)
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*/
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void __init init_arch(bp_tag_t *bp_start)
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{
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/* Parse boot parameters */
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if (bp_start)
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parse_bootparam(bp_start);
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#ifdef CONFIG_OF
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early_init_devtree(dtb_start);
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#endif
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#ifdef CONFIG_CMDLINE_BOOL
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if (!command_line[0])
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strlcpy(command_line, default_command_line, COMMAND_LINE_SIZE);
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#endif
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/* Early hook for platforms */
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platform_init(bp_start);
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/* Initialize MMU. */
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init_mmu();
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}
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/*
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* Initialize system. Setup memory and reserve regions.
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*/
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extern char _end;
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extern char _stext;
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extern char _WindowVectors_text_start;
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extern char _WindowVectors_text_end;
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extern char _DebugInterruptVector_literal_start;
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extern char _DebugInterruptVector_text_end;
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extern char _KernelExceptionVector_literal_start;
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extern char _KernelExceptionVector_text_end;
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extern char _UserExceptionVector_literal_start;
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extern char _UserExceptionVector_text_end;
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extern char _DoubleExceptionVector_literal_start;
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extern char _DoubleExceptionVector_text_end;
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#if XCHAL_EXCM_LEVEL >= 2
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extern char _Level2InterruptVector_text_start;
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extern char _Level2InterruptVector_text_end;
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#endif
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#if XCHAL_EXCM_LEVEL >= 3
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extern char _Level3InterruptVector_text_start;
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extern char _Level3InterruptVector_text_end;
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#endif
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#if XCHAL_EXCM_LEVEL >= 4
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extern char _Level4InterruptVector_text_start;
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extern char _Level4InterruptVector_text_end;
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#endif
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#if XCHAL_EXCM_LEVEL >= 5
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extern char _Level5InterruptVector_text_start;
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extern char _Level5InterruptVector_text_end;
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#endif
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#if XCHAL_EXCM_LEVEL >= 6
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extern char _Level6InterruptVector_text_start;
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extern char _Level6InterruptVector_text_end;
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#endif
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#ifdef CONFIG_SMP
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extern char _SecondaryResetVector_text_start;
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extern char _SecondaryResetVector_text_end;
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#endif
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static inline int mem_reserve(unsigned long start, unsigned long end)
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{
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return memblock_reserve(start, end - start);
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}
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void __init setup_arch(char **cmdline_p)
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{
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strlcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
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*cmdline_p = command_line;
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/* Reserve some memory regions */
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#ifdef CONFIG_BLK_DEV_INITRD
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if (initrd_start < initrd_end) {
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initrd_is_mapped = mem_reserve(__pa(initrd_start),
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__pa(initrd_end)) == 0;
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initrd_below_start_ok = 1;
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} else {
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initrd_start = 0;
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}
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#endif
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mem_reserve(__pa(&_stext), __pa(&_end));
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mem_reserve(__pa(&_WindowVectors_text_start),
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__pa(&_WindowVectors_text_end));
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mem_reserve(__pa(&_DebugInterruptVector_literal_start),
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__pa(&_DebugInterruptVector_text_end));
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mem_reserve(__pa(&_KernelExceptionVector_literal_start),
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__pa(&_KernelExceptionVector_text_end));
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mem_reserve(__pa(&_UserExceptionVector_literal_start),
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__pa(&_UserExceptionVector_text_end));
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mem_reserve(__pa(&_DoubleExceptionVector_literal_start),
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__pa(&_DoubleExceptionVector_text_end));
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#if XCHAL_EXCM_LEVEL >= 2
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mem_reserve(__pa(&_Level2InterruptVector_text_start),
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__pa(&_Level2InterruptVector_text_end));
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#endif
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#if XCHAL_EXCM_LEVEL >= 3
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mem_reserve(__pa(&_Level3InterruptVector_text_start),
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__pa(&_Level3InterruptVector_text_end));
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#endif
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#if XCHAL_EXCM_LEVEL >= 4
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mem_reserve(__pa(&_Level4InterruptVector_text_start),
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__pa(&_Level4InterruptVector_text_end));
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#endif
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#if XCHAL_EXCM_LEVEL >= 5
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mem_reserve(__pa(&_Level5InterruptVector_text_start),
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__pa(&_Level5InterruptVector_text_end));
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#endif
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#if XCHAL_EXCM_LEVEL >= 6
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mem_reserve(__pa(&_Level6InterruptVector_text_start),
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__pa(&_Level6InterruptVector_text_end));
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#endif
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#ifdef CONFIG_SMP
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mem_reserve(__pa(&_SecondaryResetVector_text_start),
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__pa(&_SecondaryResetVector_text_end));
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#endif
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parse_early_param();
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bootmem_init();
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unflatten_and_copy_device_tree();
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platform_setup(cmdline_p);
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#ifdef CONFIG_SMP
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smp_init_cpus();
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#endif
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paging_init();
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zones_init();
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#ifdef CONFIG_VT
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# if defined(CONFIG_VGA_CONSOLE)
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conswitchp = &vga_con;
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# elif defined(CONFIG_DUMMY_CONSOLE)
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conswitchp = &dummy_con;
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# endif
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#endif
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#ifdef CONFIG_PCI
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platform_pcibios_init();
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#endif
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}
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static DEFINE_PER_CPU(struct cpu, cpu_data);
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static int __init topology_init(void)
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{
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int i;
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for_each_possible_cpu(i) {
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struct cpu *cpu = &per_cpu(cpu_data, i);
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cpu->hotpluggable = !!i;
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register_cpu(cpu, i);
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}
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return 0;
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}
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subsys_initcall(topology_init);
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void cpu_reset(void)
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{
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#if XCHAL_HAVE_PTP_MMU && IS_ENABLED(CONFIG_MMU)
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local_irq_disable();
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/*
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* We have full MMU: all autoload ways, ways 7, 8 and 9 of DTLB must
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* be flushed.
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* Way 4 is not currently used by linux.
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* Ways 5 and 6 shall not be touched on MMUv2 as they are hardwired.
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* Way 5 shall be flushed and way 6 shall be set to identity mapping
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* on MMUv3.
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*/
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local_flush_tlb_all();
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invalidate_page_directory();
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#if XCHAL_HAVE_SPANNING_WAY
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/* MMU v3 */
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{
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unsigned long vaddr = (unsigned long)cpu_reset;
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unsigned long paddr = __pa(vaddr);
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unsigned long tmpaddr = vaddr + SZ_512M;
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unsigned long tmp0, tmp1, tmp2, tmp3;
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/*
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* Find a place for the temporary mapping. It must not be
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* in the same 512MB region with vaddr or paddr, otherwise
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* there may be multihit exception either on entry to the
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* temporary mapping, or on entry to the identity mapping.
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* (512MB is the biggest page size supported by TLB.)
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*/
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while (((tmpaddr ^ paddr) & -SZ_512M) == 0)
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tmpaddr += SZ_512M;
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/* Invalidate mapping in the selected temporary area */
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if (itlb_probe(tmpaddr) & 0x8)
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invalidate_itlb_entry(itlb_probe(tmpaddr));
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if (itlb_probe(tmpaddr + PAGE_SIZE) & 0x8)
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invalidate_itlb_entry(itlb_probe(tmpaddr + PAGE_SIZE));
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/*
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* Map two consecutive pages starting at the physical address
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* of this function to the temporary mapping area.
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*/
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write_itlb_entry(__pte((paddr & PAGE_MASK) |
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_PAGE_HW_VALID |
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_PAGE_HW_EXEC |
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_PAGE_CA_BYPASS),
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tmpaddr & PAGE_MASK);
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write_itlb_entry(__pte(((paddr & PAGE_MASK) + PAGE_SIZE) |
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_PAGE_HW_VALID |
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_PAGE_HW_EXEC |
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_PAGE_CA_BYPASS),
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(tmpaddr & PAGE_MASK) + PAGE_SIZE);
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/* Reinitialize TLB */
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__asm__ __volatile__ ("movi %0, 1f\n\t"
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"movi %3, 2f\n\t"
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"add %0, %0, %4\n\t"
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"add %3, %3, %5\n\t"
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"jx %0\n"
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/*
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* No literal, data or stack access
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|
* below this point
|
|
*/
|
|
"1:\n\t"
|
|
/* Initialize *tlbcfg */
|
|
"movi %0, 0\n\t"
|
|
"wsr %0, itlbcfg\n\t"
|
|
"wsr %0, dtlbcfg\n\t"
|
|
/* Invalidate TLB way 5 */
|
|
"movi %0, 4\n\t"
|
|
"movi %1, 5\n"
|
|
"1:\n\t"
|
|
"iitlb %1\n\t"
|
|
"idtlb %1\n\t"
|
|
"add %1, %1, %6\n\t"
|
|
"addi %0, %0, -1\n\t"
|
|
"bnez %0, 1b\n\t"
|
|
/* Initialize TLB way 6 */
|
|
"movi %0, 7\n\t"
|
|
"addi %1, %9, 3\n\t"
|
|
"addi %2, %9, 6\n"
|
|
"1:\n\t"
|
|
"witlb %1, %2\n\t"
|
|
"wdtlb %1, %2\n\t"
|
|
"add %1, %1, %7\n\t"
|
|
"add %2, %2, %7\n\t"
|
|
"addi %0, %0, -1\n\t"
|
|
"bnez %0, 1b\n\t"
|
|
/* Jump to identity mapping */
|
|
"jx %3\n"
|
|
"2:\n\t"
|
|
/* Complete way 6 initialization */
|
|
"witlb %1, %2\n\t"
|
|
"wdtlb %1, %2\n\t"
|
|
/* Invalidate temporary mapping */
|
|
"sub %0, %9, %7\n\t"
|
|
"iitlb %0\n\t"
|
|
"add %0, %0, %8\n\t"
|
|
"iitlb %0"
|
|
: "=&a"(tmp0), "=&a"(tmp1), "=&a"(tmp2),
|
|
"=&a"(tmp3)
|
|
: "a"(tmpaddr - vaddr),
|
|
"a"(paddr - vaddr),
|
|
"a"(SZ_128M), "a"(SZ_512M),
|
|
"a"(PAGE_SIZE),
|
|
"a"((tmpaddr + SZ_512M) & PAGE_MASK)
|
|
: "memory");
|
|
}
|
|
#endif
|
|
#endif
|
|
__asm__ __volatile__ ("movi a2, 0\n\t"
|
|
"wsr a2, icountlevel\n\t"
|
|
"movi a2, 0\n\t"
|
|
"wsr a2, icount\n\t"
|
|
#if XCHAL_NUM_IBREAK > 0
|
|
"wsr a2, ibreakenable\n\t"
|
|
#endif
|
|
#if XCHAL_HAVE_LOOPS
|
|
"wsr a2, lcount\n\t"
|
|
#endif
|
|
"movi a2, 0x1f\n\t"
|
|
"wsr a2, ps\n\t"
|
|
"isync\n\t"
|
|
"jx %0\n\t"
|
|
:
|
|
: "a" (XCHAL_RESET_VECTOR_VADDR)
|
|
: "a2");
|
|
for (;;)
|
|
;
|
|
}
|
|
|
|
void machine_restart(char * cmd)
|
|
{
|
|
platform_restart();
|
|
}
|
|
|
|
void machine_halt(void)
|
|
{
|
|
platform_halt();
|
|
while (1);
|
|
}
|
|
|
|
void machine_power_off(void)
|
|
{
|
|
platform_power_off();
|
|
while (1);
|
|
}
|
|
#ifdef CONFIG_PROC_FS
|
|
|
|
/*
|
|
* Display some core information through /proc/cpuinfo.
|
|
*/
|
|
|
|
static int
|
|
c_show(struct seq_file *f, void *slot)
|
|
{
|
|
/* high-level stuff */
|
|
seq_printf(f, "CPU count\t: %u\n"
|
|
"CPU list\t: %*pbl\n"
|
|
"vendor_id\t: Tensilica\n"
|
|
"model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
|
|
"core ID\t\t: " XCHAL_CORE_ID "\n"
|
|
"build ID\t: 0x%x\n"
|
|
"byte order\t: %s\n"
|
|
"cpu MHz\t\t: %lu.%02lu\n"
|
|
"bogomips\t: %lu.%02lu\n",
|
|
num_online_cpus(),
|
|
cpumask_pr_args(cpu_online_mask),
|
|
XCHAL_BUILD_UNIQUE_ID,
|
|
XCHAL_HAVE_BE ? "big" : "little",
|
|
ccount_freq/1000000,
|
|
(ccount_freq/10000) % 100,
|
|
loops_per_jiffy/(500000/HZ),
|
|
(loops_per_jiffy/(5000/HZ)) % 100);
|
|
|
|
seq_printf(f,"flags\t\t: "
|
|
#if XCHAL_HAVE_NMI
|
|
"nmi "
|
|
#endif
|
|
#if XCHAL_HAVE_DEBUG
|
|
"debug "
|
|
# if XCHAL_HAVE_OCD
|
|
"ocd "
|
|
# endif
|
|
#endif
|
|
#if XCHAL_HAVE_DENSITY
|
|
"density "
|
|
#endif
|
|
#if XCHAL_HAVE_BOOLEANS
|
|
"boolean "
|
|
#endif
|
|
#if XCHAL_HAVE_LOOPS
|
|
"loop "
|
|
#endif
|
|
#if XCHAL_HAVE_NSA
|
|
"nsa "
|
|
#endif
|
|
#if XCHAL_HAVE_MINMAX
|
|
"minmax "
|
|
#endif
|
|
#if XCHAL_HAVE_SEXT
|
|
"sext "
|
|
#endif
|
|
#if XCHAL_HAVE_CLAMPS
|
|
"clamps "
|
|
#endif
|
|
#if XCHAL_HAVE_MAC16
|
|
"mac16 "
|
|
#endif
|
|
#if XCHAL_HAVE_MUL16
|
|
"mul16 "
|
|
#endif
|
|
#if XCHAL_HAVE_MUL32
|
|
"mul32 "
|
|
#endif
|
|
#if XCHAL_HAVE_MUL32_HIGH
|
|
"mul32h "
|
|
#endif
|
|
#if XCHAL_HAVE_FP
|
|
"fpu "
|
|
#endif
|
|
#if XCHAL_HAVE_S32C1I
|
|
"s32c1i "
|
|
#endif
|
|
"\n");
|
|
|
|
/* Registers. */
|
|
seq_printf(f,"physical aregs\t: %d\n"
|
|
"misc regs\t: %d\n"
|
|
"ibreak\t\t: %d\n"
|
|
"dbreak\t\t: %d\n",
|
|
XCHAL_NUM_AREGS,
|
|
XCHAL_NUM_MISC_REGS,
|
|
XCHAL_NUM_IBREAK,
|
|
XCHAL_NUM_DBREAK);
|
|
|
|
|
|
/* Interrupt. */
|
|
seq_printf(f,"num ints\t: %d\n"
|
|
"ext ints\t: %d\n"
|
|
"int levels\t: %d\n"
|
|
"timers\t\t: %d\n"
|
|
"debug level\t: %d\n",
|
|
XCHAL_NUM_INTERRUPTS,
|
|
XCHAL_NUM_EXTINTERRUPTS,
|
|
XCHAL_NUM_INTLEVELS,
|
|
XCHAL_NUM_TIMERS,
|
|
XCHAL_DEBUGLEVEL);
|
|
|
|
/* Cache */
|
|
seq_printf(f,"icache line size: %d\n"
|
|
"icache ways\t: %d\n"
|
|
"icache size\t: %d\n"
|
|
"icache flags\t: "
|
|
#if XCHAL_ICACHE_LINE_LOCKABLE
|
|
"lock "
|
|
#endif
|
|
"\n"
|
|
"dcache line size: %d\n"
|
|
"dcache ways\t: %d\n"
|
|
"dcache size\t: %d\n"
|
|
"dcache flags\t: "
|
|
#if XCHAL_DCACHE_IS_WRITEBACK
|
|
"writeback "
|
|
#endif
|
|
#if XCHAL_DCACHE_LINE_LOCKABLE
|
|
"lock "
|
|
#endif
|
|
"\n",
|
|
XCHAL_ICACHE_LINESIZE,
|
|
XCHAL_ICACHE_WAYS,
|
|
XCHAL_ICACHE_SIZE,
|
|
XCHAL_DCACHE_LINESIZE,
|
|
XCHAL_DCACHE_WAYS,
|
|
XCHAL_DCACHE_SIZE);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* We show only CPU #0 info.
|
|
*/
|
|
static void *
|
|
c_start(struct seq_file *f, loff_t *pos)
|
|
{
|
|
return (*pos == 0) ? (void *)1 : NULL;
|
|
}
|
|
|
|
static void *
|
|
c_next(struct seq_file *f, void *v, loff_t *pos)
|
|
{
|
|
return NULL;
|
|
}
|
|
|
|
static void
|
|
c_stop(struct seq_file *f, void *v)
|
|
{
|
|
}
|
|
|
|
const struct seq_operations cpuinfo_op =
|
|
{
|
|
.start = c_start,
|
|
.next = c_next,
|
|
.stop = c_stop,
|
|
.show = c_show,
|
|
};
|
|
|
|
#endif /* CONFIG_PROC_FS */
|