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caa5171622
Based on replies to a respective query, remove the pci_dac_dma_...() APIs (except for pci_dac_dma_supported() on Alpha, where this function is used in non-DAC PCI DMA code). Signed-off-by: Jan Beulich <jbeulich@novell.com> Cc: Andi Kleen <ak@suse.de> Cc: Jesse Barnes <jesse.barnes@intel.com> Cc: Christoph Hellwig <hch@infradead.org> Acked-by: David Miller <davem@davemloft.net> Cc: Jeff Garzik <jeff@garzik.org> Cc: <linux-arch@vger.kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
85 lines
2.3 KiB
C
85 lines
2.3 KiB
C
/*
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* include/asm-v850/rte_cb.h -- Midas labs RTE-CB series of evaluation boards
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*
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* Copyright (C) 2001,02,03 NEC Electronics Corporation
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* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*
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* Written by Miles Bader <miles@gnu.org>
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*/
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#ifndef __V850_RTE_CB_H__
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#define __V850_RTE_CB_H__
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/* The SRAM on the Mother-A motherboard. */
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#define MB_A_SRAM_ADDR GCS0_ADDR
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#define MB_A_SRAM_SIZE 0x00200000 /* 2MB */
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#ifdef CONFIG_RTE_GBUS_INT
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/* GBUS interrupt support. */
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# include <asm/gbus_int.h>
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# define GBUS_INT_BASE_IRQ NUM_RTE_CB_IRQS
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# define GBUS_INT_BASE_ADDR (GCS2_ADDR + 0x00006000)
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/* Some specific interrupts. */
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# define IRQ_MB_A_LAN IRQ_GBUS_INT(10)
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# define IRQ_MB_A_PCI1(n) (IRQ_GBUS_INT(16) + (n))
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# define IRQ_MB_A_PCI1_NUM 4
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# define IRQ_MB_A_PCI2(n) (IRQ_GBUS_INT(20) + (n))
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# define IRQ_MB_A_PCI2_NUM 4
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# define IRQ_MB_A_EXT(n) (IRQ_GBUS_INT(24) + (n))
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# define IRQ_MB_A_EXT_NUM 4
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# define IRQ_MB_A_USB_OC(n) (IRQ_GBUS_INT(28) + (n))
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# define IRQ_MB_A_USB_OC_NUM 2
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# define IRQ_MB_A_PCMCIA_OC IRQ_GBUS_INT(30)
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/* We define NUM_MACH_IRQS to include extra interrupts from the GBUS. */
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# define NUM_MACH_IRQS (NUM_RTE_CB_IRQS + IRQ_GBUS_INT_NUM)
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#else /* !CONFIG_RTE_GBUS_INT */
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# define NUM_MACH_IRQS NUM_RTE_CB_IRQS
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#endif /* CONFIG_RTE_GBUS_INT */
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#ifdef CONFIG_RTE_MB_A_PCI
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/* Mother-A PCI bus support. */
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# include <asm/rte_mb_a_pci.h>
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/* These are the base addresses used for allocating device address
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space. 512K of the motherboard SRAM is in the same space, so we have
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to be careful not to let it be allocated. */
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# define PCIBIOS_MIN_MEM (MB_A_PCI_MEM_ADDR + 0x80000)
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# define PCIBIOS_MIN_IO MB_A_PCI_IO_ADDR
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/* As we don't really support PCI DMA to cpu memory, and use bounce-buffers
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instead, perversely enough, this becomes always true! */
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# define pci_dma_supported(dev, mask) 1
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# define pcibios_assign_all_busses() 1
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#endif /* CONFIG_RTE_MB_A_PCI */
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/* For <asm/param.h> */
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#ifndef HZ
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#define HZ 100
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#endif
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#ifndef __ASSEMBLY__
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extern void rte_cb_early_init (void);
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extern void rte_cb_init_irqs (void);
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#endif /* !__ASSEMBLY__ */
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#endif /* __V850_RTE_CB_H__ */
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