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1ef48a262b
Even though the DMA engine infrastructure has support for multiple channels per device, the mv_xor driver registers one DMA engine device for each channel, because the mv_xor channels inside the same XOR engine have different capabilities, and the DMA engine infrastructure only allows to express capabilities at the DMA engine device level. The mv_xor driver has therefore been registering one DMA engine device and one DMA engine channel for each XOR channel since its introduction in the kernel. However, it kept two separate internal structures, mv_xor_device and mv_xor_channel, which didn't make a lot of sense since there was a 1:1 mapping between those structures. This patch gets rid of this duplication, and merges everything into the mv_xor_chan structure. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
170 lines
5.8 KiB
C
170 lines
5.8 KiB
C
/*
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* Copyright (C) 2007, 2008, Marvell International Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#ifndef MV_XOR_H
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#define MV_XOR_H
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#include <linux/types.h>
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#include <linux/io.h>
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#include <linux/dmaengine.h>
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#include <linux/interrupt.h>
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#define USE_TIMER
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#define MV_XOR_SLOT_SIZE 64
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#define MV_XOR_THRESHOLD 1
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#define MV_XOR_MAX_CHANNELS 2
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#define XOR_OPERATION_MODE_XOR 0
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#define XOR_OPERATION_MODE_MEMCPY 2
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#define XOR_OPERATION_MODE_MEMSET 4
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#define XOR_CURR_DESC(chan) (chan->mmr_base + 0x210 + (chan->idx * 4))
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#define XOR_NEXT_DESC(chan) (chan->mmr_base + 0x200 + (chan->idx * 4))
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#define XOR_BYTE_COUNT(chan) (chan->mmr_base + 0x220 + (chan->idx * 4))
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#define XOR_DEST_POINTER(chan) (chan->mmr_base + 0x2B0 + (chan->idx * 4))
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#define XOR_BLOCK_SIZE(chan) (chan->mmr_base + 0x2C0 + (chan->idx * 4))
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#define XOR_INIT_VALUE_LOW(chan) (chan->mmr_base + 0x2E0)
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#define XOR_INIT_VALUE_HIGH(chan) (chan->mmr_base + 0x2E4)
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#define XOR_CONFIG(chan) (chan->mmr_base + 0x10 + (chan->idx * 4))
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#define XOR_ACTIVATION(chan) (chan->mmr_base + 0x20 + (chan->idx * 4))
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#define XOR_INTR_CAUSE(chan) (chan->mmr_base + 0x30)
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#define XOR_INTR_MASK(chan) (chan->mmr_base + 0x40)
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#define XOR_ERROR_CAUSE(chan) (chan->mmr_base + 0x50)
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#define XOR_ERROR_ADDR(chan) (chan->mmr_base + 0x60)
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#define XOR_INTR_MASK_VALUE 0x3F5
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#define WINDOW_BASE(w) (0x250 + ((w) << 2))
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#define WINDOW_SIZE(w) (0x270 + ((w) << 2))
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#define WINDOW_REMAP_HIGH(w) (0x290 + ((w) << 2))
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#define WINDOW_BAR_ENABLE(chan) (0x240 + ((chan) << 2))
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struct mv_xor_private {
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void __iomem *xor_base;
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void __iomem *xor_high_base;
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struct clk *clk;
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struct mv_xor_chan *channels[MV_XOR_MAX_CHANNELS];
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};
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/**
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* struct mv_xor_chan - internal representation of a XOR channel
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* @pending: allows batching of hardware operations
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* @lock: serializes enqueue/dequeue operations to the descriptors pool
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* @mmr_base: memory mapped register base
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* @idx: the index of the xor channel
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* @chain: device chain view of the descriptors
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* @completed_slots: slots completed by HW but still need to be acked
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* @device: parent device
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* @common: common dmaengine channel object members
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* @last_used: place holder for allocation to continue from where it left off
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* @all_slots: complete domain of slots usable by the channel
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* @slots_allocated: records the actual size of the descriptor slot pool
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* @irq_tasklet: bottom half where mv_xor_slot_cleanup runs
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*/
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struct mv_xor_chan {
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int pending;
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spinlock_t lock; /* protects the descriptor slot pool */
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void __iomem *mmr_base;
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unsigned int idx;
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enum dma_transaction_type current_type;
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struct list_head chain;
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struct list_head completed_slots;
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dma_addr_t dma_desc_pool;
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void *dma_desc_pool_virt;
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size_t pool_size;
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struct dma_device dmadev;
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struct mv_xor_private *shared;
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struct dma_chan dmachan;
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struct mv_xor_desc_slot *last_used;
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struct list_head all_slots;
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int slots_allocated;
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struct tasklet_struct irq_tasklet;
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#ifdef USE_TIMER
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unsigned long cleanup_time;
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u32 current_on_last_cleanup;
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#endif
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};
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/**
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* struct mv_xor_desc_slot - software descriptor
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* @slot_node: node on the mv_xor_chan.all_slots list
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* @chain_node: node on the mv_xor_chan.chain list
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* @completed_node: node on the mv_xor_chan.completed_slots list
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* @hw_desc: virtual address of the hardware descriptor chain
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* @phys: hardware address of the hardware descriptor chain
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* @group_head: first operation in a transaction
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* @slot_cnt: total slots used in an transaction (group of operations)
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* @slots_per_op: number of slots per operation
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* @idx: pool index
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* @unmap_src_cnt: number of xor sources
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* @unmap_len: transaction bytecount
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* @tx_list: list of slots that make up a multi-descriptor transaction
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* @async_tx: support for the async_tx api
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* @xor_check_result: result of zero sum
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* @crc32_result: result crc calculation
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*/
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struct mv_xor_desc_slot {
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struct list_head slot_node;
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struct list_head chain_node;
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struct list_head completed_node;
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enum dma_transaction_type type;
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void *hw_desc;
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struct mv_xor_desc_slot *group_head;
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u16 slot_cnt;
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u16 slots_per_op;
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u16 idx;
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u16 unmap_src_cnt;
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u32 value;
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size_t unmap_len;
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struct list_head tx_list;
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struct dma_async_tx_descriptor async_tx;
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union {
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u32 *xor_check_result;
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u32 *crc32_result;
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};
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#ifdef USE_TIMER
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unsigned long arrival_time;
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struct timer_list timeout;
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#endif
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};
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/* This structure describes XOR descriptor size 64bytes */
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struct mv_xor_desc {
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u32 status; /* descriptor execution status */
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u32 crc32_result; /* result of CRC-32 calculation */
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u32 desc_command; /* type of operation to be carried out */
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u32 phy_next_desc; /* next descriptor address pointer */
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u32 byte_count; /* size of src/dst blocks in bytes */
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u32 phy_dest_addr; /* destination block address */
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u32 phy_src_addr[8]; /* source block addresses */
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u32 reserved0;
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u32 reserved1;
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};
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#define to_mv_sw_desc(addr_hw_desc) \
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container_of(addr_hw_desc, struct mv_xor_desc_slot, hw_desc)
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#define mv_hw_desc_slot_idx(hw_desc, idx) \
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((void *)(((unsigned long)hw_desc) + ((idx) << 5)))
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#define MV_XOR_MIN_BYTE_COUNT (128)
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#define XOR_MAX_BYTE_COUNT ((16 * 1024 * 1024) - 1)
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#define MV_XOR_MAX_BYTE_COUNT XOR_MAX_BYTE_COUNT
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#endif
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