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https://github.com/edk2-porting/linux-next.git
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a6dbba77a9
This patch adds on-chip PCI bridge support for the PQ2 family. The incomplete existent code is updated with interrupt handling stuff and board-specific bits for 8272ADS and PQ2FADS; the related files were renamed (from m8260_pci to m82xx_pci) to be of more generic fashion. This is tested with 8266ADS and 8272ADS, should work on PQ2FADS as well. Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
188 lines
5.9 KiB
C
188 lines
5.9 KiB
C
/*
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* include/asm-ppc/m8260_pci.h
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*
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* Definitions for the MPC8250/MPC8265/MPC8266 integrated PCI host bridge.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifdef __KERNEL__
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#ifndef __M8260_PCI_H
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#define __M8260_PCI_H
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#include <linux/pci_ids.h>
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/*
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* Define the vendor/device ID for the MPC8265.
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*/
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#define PCI_DEVICE_ID_MPC8265 ((0x18C0 << 16) | PCI_VENDOR_ID_MOTOROLA)
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#define PCI_DEVICE_ID_MPC8272 ((0x18C1 << 16) | PCI_VENDOR_ID_MOTOROLA)
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#define M8265_PCIBR0 0x101ac
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#define M8265_PCIBR1 0x101b0
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#define M8265_PCIMSK0 0x101c4
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#define M8265_PCIMSK1 0x101c8
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/* Bit definitions for PCIBR registers */
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#define PCIBR_ENABLE 0x00000001
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/* Bit definitions for PCIMSK registers */
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#define PCIMSK_32KiB 0xFFFF8000 /* Size of window, smallest */
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#define PCIMSK_64KiB 0xFFFF0000
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#define PCIMSK_128KiB 0xFFFE0000
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#define PCIMSK_256KiB 0xFFFC0000
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#define PCIMSK_512KiB 0xFFF80000
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#define PCIMSK_1MiB 0xFFF00000
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#define PCIMSK_2MiB 0xFFE00000
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#define PCIMSK_4MiB 0xFFC00000
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#define PCIMSK_8MiB 0xFF800000
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#define PCIMSK_16MiB 0xFF000000
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#define PCIMSK_32MiB 0xFE000000
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#define PCIMSK_64MiB 0xFC000000
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#define PCIMSK_128MiB 0xF8000000
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#define PCIMSK_256MiB 0xF0000000
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#define PCIMSK_512MiB 0xE0000000
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#define PCIMSK_1GiB 0xC0000000 /* Size of window, largest */
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#define M826X_SCCR_PCI_MODE_EN 0x100
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/*
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* Outbound ATU registers (3 sets). These registers control how 60x bus (local)
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* addresses are translated to PCI addresses when the MPC826x is a PCI bus
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* master (initiator).
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*/
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#define POTAR_REG0 0x10800 /* PCI Outbound Translation Addr registers */
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#define POTAR_REG1 0x10818
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#define POTAR_REG2 0x10830
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#define POBAR_REG0 0x10808 /* PCI Outbound Base Addr registers */
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#define POBAR_REG1 0x10820
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#define POBAR_REG2 0x10838
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#define POCMR_REG0 0x10810 /* PCI Outbound Comparison Mask registers */
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#define POCMR_REG1 0x10828
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#define POCMR_REG2 0x10840
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/* Bit definitions for POMCR registers */
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#define POCMR_MASK_4KiB 0x000FFFFF
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#define POCMR_MASK_8KiB 0x000FFFFE
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#define POCMR_MASK_16KiB 0x000FFFFC
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#define POCMR_MASK_32KiB 0x000FFFF8
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#define POCMR_MASK_64KiB 0x000FFFF0
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#define POCMR_MASK_128KiB 0x000FFFE0
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#define POCMR_MASK_256KiB 0x000FFFC0
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#define POCMR_MASK_512KiB 0x000FFF80
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#define POCMR_MASK_1MiB 0x000FFF00
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#define POCMR_MASK_2MiB 0x000FFE00
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#define POCMR_MASK_4MiB 0x000FFC00
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#define POCMR_MASK_8MiB 0x000FF800
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#define POCMR_MASK_16MiB 0x000FF000
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#define POCMR_MASK_32MiB 0x000FE000
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#define POCMR_MASK_64MiB 0x000FC000
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#define POCMR_MASK_128MiB 0x000F8000
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#define POCMR_MASK_256MiB 0x000F0000
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#define POCMR_MASK_512MiB 0x000E0000
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#define POCMR_MASK_1GiB 0x000C0000
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#define POCMR_ENABLE 0x80000000
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#define POCMR_PCI_IO 0x40000000
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#define POCMR_PREFETCH_EN 0x20000000
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/* Soft PCI reset */
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#define PCI_GCR_REG 0x10880
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/* Bit definitions for PCI_GCR registers */
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#define PCIGCR_PCI_BUS_EN 0x1
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#define PCI_EMR_REG 0x10888
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/*
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* Inbound ATU registers (2 sets). These registers control how PCI addresses
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* are translated to 60x bus (local) addresses when the MPC826x is a PCI bus target.
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*/
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#define PITAR_REG1 0x108D0
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#define PIBAR_REG1 0x108D8
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#define PICMR_REG1 0x108E0
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#define PITAR_REG0 0x108E8
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#define PIBAR_REG0 0x108F0
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#define PICMR_REG0 0x108F8
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/* Bit definitions for PCI Inbound Comparison Mask registers */
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#define PICMR_MASK_4KiB 0x000FFFFF
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#define PICMR_MASK_8KiB 0x000FFFFE
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#define PICMR_MASK_16KiB 0x000FFFFC
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#define PICMR_MASK_32KiB 0x000FFFF8
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#define PICMR_MASK_64KiB 0x000FFFF0
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#define PICMR_MASK_128KiB 0x000FFFE0
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#define PICMR_MASK_256KiB 0x000FFFC0
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#define PICMR_MASK_512KiB 0x000FFF80
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#define PICMR_MASK_1MiB 0x000FFF00
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#define PICMR_MASK_2MiB 0x000FFE00
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#define PICMR_MASK_4MiB 0x000FFC00
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#define PICMR_MASK_8MiB 0x000FF800
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#define PICMR_MASK_16MiB 0x000FF000
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#define PICMR_MASK_32MiB 0x000FE000
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#define PICMR_MASK_64MiB 0x000FC000
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#define PICMR_MASK_128MiB 0x000F8000
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#define PICMR_MASK_256MiB 0x000F0000
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#define PICMR_MASK_512MiB 0x000E0000
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#define PICMR_MASK_1GiB 0x000C0000
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#define PICMR_ENABLE 0x80000000
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#define PICMR_NO_SNOOP_EN 0x40000000
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#define PICMR_PREFETCH_EN 0x20000000
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/* PCI error Registers */
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#define PCI_ERROR_STATUS_REG 0x10884
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#define PCI_ERROR_MASK_REG 0x10888
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#define PCI_ERROR_CONTROL_REG 0x1088C
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#define PCI_ERROR_ADRS_CAPTURE_REG 0x10890
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#define PCI_ERROR_DATA_CAPTURE_REG 0x10898
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#define PCI_ERROR_CTRL_CAPTURE_REG 0x108A0
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/* PCI error Register bit defines */
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#define PCI_ERROR_PCI_ADDR_PAR 0x00000001
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#define PCI_ERROR_PCI_DATA_PAR_WR 0x00000002
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#define PCI_ERROR_PCI_DATA_PAR_RD 0x00000004
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#define PCI_ERROR_PCI_NO_RSP 0x00000008
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#define PCI_ERROR_PCI_TAR_ABT 0x00000010
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#define PCI_ERROR_PCI_SERR 0x00000020
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#define PCI_ERROR_PCI_PERR_RD 0x00000040
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#define PCI_ERROR_PCI_PERR_WR 0x00000080
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#define PCI_ERROR_I2O_OFQO 0x00000100
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#define PCI_ERROR_I2O_IPQO 0x00000200
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#define PCI_ERROR_IRA 0x00000400
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#define PCI_ERROR_NMI 0x00000800
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#define PCI_ERROR_I2O_DBMC 0x00001000
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/*
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* Register pair used to generate configuration cycles on the PCI bus
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* and access the MPC826x's own PCI configuration registers.
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*/
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#define PCI_CFG_ADDR_REG 0x10900
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#define PCI_CFG_DATA_REG 0x10904
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/* Bus parking decides where the bus control sits when idle */
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/* If modifying memory controllers for PCI park on the core */
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#define PPC_ACR_BUS_PARK_CORE 0x6
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#define PPC_ACR_BUS_PARK_PCI 0x3
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#endif /* __M8260_PCI_H */
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#endif /* __KERNEL__ */
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