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ea5a08cfa5
We don't know yet when to restore it, implement just reading. We found out what for are that PHY ops by comparing HT with N code. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
66 lines
2.1 KiB
C
66 lines
2.1 KiB
C
#ifndef B43_PHY_HT_H_
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#define B43_PHY_HT_H_
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#include "phy_common.h"
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#define B43_PHY_HT_BBCFG 0x001 /* BB config */
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#define B43_PHY_HT_BBCFG_RSTCCA 0x4000 /* Reset CCA */
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#define B43_PHY_HT_BBCFG_RSTRX 0x8000 /* Reset RX */
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#define B43_PHY_HT_BANDCTL 0x009 /* Band control */
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#define B43_PHY_HT_BANDCTL_5GHZ 0x0001 /* Use the 5GHz band */
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#define B43_PHY_HT_TABLE_ADDR 0x072 /* Table address */
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#define B43_PHY_HT_TABLE_DATALO 0x073 /* Table data low */
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#define B43_PHY_HT_TABLE_DATAHI 0x074 /* Table data high */
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#define B43_PHY_HT_BW1 0x1CE
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#define B43_PHY_HT_BW2 0x1CF
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#define B43_PHY_HT_BW3 0x1D0
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#define B43_PHY_HT_BW4 0x1D1
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#define B43_PHY_HT_BW5 0x1D2
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#define B43_PHY_HT_BW6 0x1D3
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#define B43_PHY_HT_C1_CLIP1THRES B43_PHY_OFDM(0x00E)
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#define B43_PHY_HT_C2_CLIP1THRES B43_PHY_OFDM(0x04E)
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#define B43_PHY_HT_C3_CLIP1THRES B43_PHY_OFDM(0x08E)
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#define B43_PHY_HT_RF_SEQ_MODE B43_PHY_EXTG(0x000)
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#define B43_PHY_HT_RF_SEQ_TRIG B43_PHY_EXTG(0x003)
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#define B43_PHY_HT_RF_SEQ_TRIG_RX2TX 0x0001 /* RX2TX */
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#define B43_PHY_HT_RF_SEQ_TRIG_TX2RX 0x0002 /* TX2RX */
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#define B43_PHY_HT_RF_SEQ_TRIG_UPGH 0x0004 /* Update gain H */
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#define B43_PHY_HT_RF_SEQ_TRIG_UPGL 0x0008 /* Update gain L */
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#define B43_PHY_HT_RF_SEQ_TRIG_UPGU 0x0010 /* Update gain U */
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#define B43_PHY_HT_RF_SEQ_TRIG_RST2RX 0x0020 /* Reset to RX */
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#define B43_PHY_HT_RF_SEQ_STATUS B43_PHY_EXTG(0x004)
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/* Values for the status are the same as for the trigger */
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#define B43_PHY_HT_RF_CTL1 B43_PHY_EXTG(0x010)
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#define B43_PHY_HT_AFE_CTL1 B43_PHY_EXTG(0x110)
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#define B43_PHY_HT_AFE_CTL2 B43_PHY_EXTG(0x111)
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#define B43_PHY_HT_AFE_CTL3 B43_PHY_EXTG(0x114)
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#define B43_PHY_HT_AFE_CTL4 B43_PHY_EXTG(0x115)
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#define B43_PHY_HT_AFE_CTL5 B43_PHY_EXTG(0x118)
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#define B43_PHY_HT_AFE_CTL6 B43_PHY_EXTG(0x119)
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/* Values for PHY registers used on channel switching */
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struct b43_phy_ht_channeltab_e_phy {
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u16 bw1;
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u16 bw2;
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u16 bw3;
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u16 bw4;
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u16 bw5;
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u16 bw6;
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};
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struct b43_phy_ht {
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};
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struct b43_phy_operations;
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extern const struct b43_phy_operations b43_phyops_ht;
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#endif /* B43_PHY_HT_H_ */
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