mirror of
https://github.com/edk2-porting/linux-next.git
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1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
374 lines
9.7 KiB
C
374 lines
9.7 KiB
C
/*
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* Copyright (C) 2004 IBM Corporation
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*
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* Authors:
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* Leendert van Doorn <leendert@watson.ibm.com>
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* Dave Safford <safford@watson.ibm.com>
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* Reiner Sailer <sailer@watson.ibm.com>
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* Kylene Hall <kjhall@us.ibm.com>
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*
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* Maintained by: <tpmdd_devel@lists.sourceforge.net>
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*
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* Device driver for TCG/TCPA TPM (trusted platform module).
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* Specifications at www.trustedcomputinggroup.org
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation, version 2 of the
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* License.
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*
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*/
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#include "tpm.h"
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/* National definitions */
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#define TPM_NSC_BASE 0x360
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#define TPM_NSC_IRQ 0x07
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#define NSC_LDN_INDEX 0x07
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#define NSC_SID_INDEX 0x20
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#define NSC_LDC_INDEX 0x30
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#define NSC_DIO_INDEX 0x60
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#define NSC_CIO_INDEX 0x62
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#define NSC_IRQ_INDEX 0x70
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#define NSC_ITS_INDEX 0x71
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#define NSC_STATUS 0x01
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#define NSC_COMMAND 0x01
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#define NSC_DATA 0x00
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/* status bits */
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#define NSC_STATUS_OBF 0x01 /* output buffer full */
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#define NSC_STATUS_IBF 0x02 /* input buffer full */
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#define NSC_STATUS_F0 0x04 /* F0 */
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#define NSC_STATUS_A2 0x08 /* A2 */
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#define NSC_STATUS_RDY 0x10 /* ready to receive command */
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#define NSC_STATUS_IBR 0x20 /* ready to receive data */
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/* command bits */
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#define NSC_COMMAND_NORMAL 0x01 /* normal mode */
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#define NSC_COMMAND_EOC 0x03
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#define NSC_COMMAND_CANCEL 0x22
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/*
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* Wait for a certain status to appear
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*/
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static int wait_for_stat(struct tpm_chip *chip, u8 mask, u8 val, u8 * data)
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{
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int expired = 0;
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struct timer_list status_timer =
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TIMER_INITIALIZER(tpm_time_expired, jiffies + 10 * HZ,
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(unsigned long) &expired);
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/* status immediately available check */
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*data = inb(chip->vendor->base + NSC_STATUS);
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if ((*data & mask) == val)
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return 0;
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/* wait for status */
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add_timer(&status_timer);
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do {
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set_current_state(TASK_UNINTERRUPTIBLE);
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schedule_timeout(TPM_TIMEOUT);
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*data = inb(chip->vendor->base + 1);
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if ((*data & mask) == val) {
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del_singleshot_timer_sync(&status_timer);
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return 0;
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}
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}
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while (!expired);
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return -EBUSY;
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}
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static int nsc_wait_for_ready(struct tpm_chip *chip)
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{
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int status;
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int expired = 0;
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struct timer_list status_timer =
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TIMER_INITIALIZER(tpm_time_expired, jiffies + 100,
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(unsigned long) &expired);
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/* status immediately available check */
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status = inb(chip->vendor->base + NSC_STATUS);
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if (status & NSC_STATUS_OBF)
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status = inb(chip->vendor->base + NSC_DATA);
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if (status & NSC_STATUS_RDY)
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return 0;
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/* wait for status */
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add_timer(&status_timer);
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do {
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set_current_state(TASK_UNINTERRUPTIBLE);
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schedule_timeout(TPM_TIMEOUT);
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status = inb(chip->vendor->base + NSC_STATUS);
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if (status & NSC_STATUS_OBF)
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status = inb(chip->vendor->base + NSC_DATA);
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if (status & NSC_STATUS_RDY) {
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del_singleshot_timer_sync(&status_timer);
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return 0;
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}
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}
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while (!expired);
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dev_info(&chip->pci_dev->dev, "wait for ready failed\n");
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return -EBUSY;
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}
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static int tpm_nsc_recv(struct tpm_chip *chip, u8 * buf, size_t count)
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{
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u8 *buffer = buf;
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u8 data, *p;
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u32 size;
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__be32 *native_size;
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if (count < 6)
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return -EIO;
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if (wait_for_stat(chip, NSC_STATUS_F0, NSC_STATUS_F0, &data) < 0) {
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dev_err(&chip->pci_dev->dev, "F0 timeout\n");
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return -EIO;
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}
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if ((data =
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inb(chip->vendor->base + NSC_DATA)) != NSC_COMMAND_NORMAL) {
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dev_err(&chip->pci_dev->dev, "not in normal mode (0x%x)\n",
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data);
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return -EIO;
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}
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/* read the whole packet */
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for (p = buffer; p < &buffer[count]; p++) {
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if (wait_for_stat
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(chip, NSC_STATUS_OBF, NSC_STATUS_OBF, &data) < 0) {
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dev_err(&chip->pci_dev->dev,
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"OBF timeout (while reading data)\n");
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return -EIO;
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}
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if (data & NSC_STATUS_F0)
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break;
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*p = inb(chip->vendor->base + NSC_DATA);
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}
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if ((data & NSC_STATUS_F0) == 0) {
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dev_err(&chip->pci_dev->dev, "F0 not set\n");
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return -EIO;
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}
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if ((data = inb(chip->vendor->base + NSC_DATA)) != NSC_COMMAND_EOC) {
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dev_err(&chip->pci_dev->dev,
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"expected end of command(0x%x)\n", data);
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return -EIO;
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}
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native_size = (__force __be32 *) (buf + 2);
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size = be32_to_cpu(*native_size);
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if (count < size)
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return -EIO;
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return size;
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}
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static int tpm_nsc_send(struct tpm_chip *chip, u8 * buf, size_t count)
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{
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u8 data;
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int i;
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/*
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* If we hit the chip with back to back commands it locks up
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* and never set IBF. Hitting it with this "hammer" seems to
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* fix it. Not sure why this is needed, we followed the flow
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* chart in the manual to the letter.
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*/
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outb(NSC_COMMAND_CANCEL, chip->vendor->base + NSC_COMMAND);
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if (nsc_wait_for_ready(chip) != 0)
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return -EIO;
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if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
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dev_err(&chip->pci_dev->dev, "IBF timeout\n");
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return -EIO;
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}
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outb(NSC_COMMAND_NORMAL, chip->vendor->base + NSC_COMMAND);
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if (wait_for_stat(chip, NSC_STATUS_IBR, NSC_STATUS_IBR, &data) < 0) {
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dev_err(&chip->pci_dev->dev, "IBR timeout\n");
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return -EIO;
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}
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for (i = 0; i < count; i++) {
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if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
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dev_err(&chip->pci_dev->dev,
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"IBF timeout (while writing data)\n");
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return -EIO;
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}
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outb(buf[i], chip->vendor->base + NSC_DATA);
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}
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if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
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dev_err(&chip->pci_dev->dev, "IBF timeout\n");
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return -EIO;
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}
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outb(NSC_COMMAND_EOC, chip->vendor->base + NSC_COMMAND);
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return count;
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}
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static void tpm_nsc_cancel(struct tpm_chip *chip)
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{
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outb(NSC_COMMAND_CANCEL, chip->vendor->base + NSC_COMMAND);
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}
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static struct file_operations nsc_ops = {
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.owner = THIS_MODULE,
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.llseek = no_llseek,
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.open = tpm_open,
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.read = tpm_read,
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.write = tpm_write,
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.release = tpm_release,
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};
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static struct tpm_vendor_specific tpm_nsc = {
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.recv = tpm_nsc_recv,
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.send = tpm_nsc_send,
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.cancel = tpm_nsc_cancel,
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.req_complete_mask = NSC_STATUS_OBF,
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.req_complete_val = NSC_STATUS_OBF,
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.base = TPM_NSC_BASE,
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.miscdev = { .fops = &nsc_ops, },
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};
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static int __devinit tpm_nsc_init(struct pci_dev *pci_dev,
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const struct pci_device_id *pci_id)
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{
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int rc = 0;
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if (pci_enable_device(pci_dev))
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return -EIO;
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if (tpm_lpc_bus_init(pci_dev, TPM_NSC_BASE)) {
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rc = -ENODEV;
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goto out_err;
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}
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/* verify that it is a National part (SID) */
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if (tpm_read_index(NSC_SID_INDEX) != 0xEF) {
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rc = -ENODEV;
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goto out_err;
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}
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dev_dbg(&pci_dev->dev, "NSC TPM detected\n");
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dev_dbg(&pci_dev->dev,
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"NSC LDN 0x%x, SID 0x%x, SRID 0x%x\n",
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tpm_read_index(0x07), tpm_read_index(0x20),
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tpm_read_index(0x27));
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dev_dbg(&pci_dev->dev,
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"NSC SIOCF1 0x%x SIOCF5 0x%x SIOCF6 0x%x SIOCF8 0x%x\n",
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tpm_read_index(0x21), tpm_read_index(0x25),
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tpm_read_index(0x26), tpm_read_index(0x28));
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dev_dbg(&pci_dev->dev, "NSC IO Base0 0x%x\n",
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(tpm_read_index(0x60) << 8) | tpm_read_index(0x61));
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dev_dbg(&pci_dev->dev, "NSC IO Base1 0x%x\n",
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(tpm_read_index(0x62) << 8) | tpm_read_index(0x63));
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dev_dbg(&pci_dev->dev, "NSC Interrupt number and wakeup 0x%x\n",
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tpm_read_index(0x70));
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dev_dbg(&pci_dev->dev, "NSC IRQ type select 0x%x\n",
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tpm_read_index(0x71));
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dev_dbg(&pci_dev->dev,
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"NSC DMA channel select0 0x%x, select1 0x%x\n",
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tpm_read_index(0x74), tpm_read_index(0x75));
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dev_dbg(&pci_dev->dev,
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"NSC Config "
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"0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
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tpm_read_index(0xF0), tpm_read_index(0xF1),
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tpm_read_index(0xF2), tpm_read_index(0xF3),
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tpm_read_index(0xF4), tpm_read_index(0xF5),
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tpm_read_index(0xF6), tpm_read_index(0xF7),
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tpm_read_index(0xF8), tpm_read_index(0xF9));
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dev_info(&pci_dev->dev,
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"NSC PC21100 TPM revision %d\n",
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tpm_read_index(0x27) & 0x1F);
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if (tpm_read_index(NSC_LDC_INDEX) == 0)
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dev_info(&pci_dev->dev, ": NSC TPM not active\n");
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/* select PM channel 1 */
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tpm_write_index(NSC_LDN_INDEX, 0x12);
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tpm_read_index(NSC_LDN_INDEX);
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/* disable the DPM module */
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tpm_write_index(NSC_LDC_INDEX, 0);
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tpm_read_index(NSC_LDC_INDEX);
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/* set the data register base addresses */
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tpm_write_index(NSC_DIO_INDEX, TPM_NSC_BASE >> 8);
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tpm_write_index(NSC_DIO_INDEX + 1, TPM_NSC_BASE);
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tpm_read_index(NSC_DIO_INDEX);
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tpm_read_index(NSC_DIO_INDEX + 1);
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/* set the command register base addresses */
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tpm_write_index(NSC_CIO_INDEX, (TPM_NSC_BASE + 1) >> 8);
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tpm_write_index(NSC_CIO_INDEX + 1, (TPM_NSC_BASE + 1));
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tpm_read_index(NSC_DIO_INDEX);
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tpm_read_index(NSC_DIO_INDEX + 1);
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/* set the interrupt number to be used for the host interface */
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tpm_write_index(NSC_IRQ_INDEX, TPM_NSC_IRQ);
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tpm_write_index(NSC_ITS_INDEX, 0x00);
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tpm_read_index(NSC_IRQ_INDEX);
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/* enable the DPM module */
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tpm_write_index(NSC_LDC_INDEX, 0x01);
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tpm_read_index(NSC_LDC_INDEX);
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if ((rc = tpm_register_hardware(pci_dev, &tpm_nsc)) < 0)
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goto out_err;
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return 0;
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out_err:
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pci_disable_device(pci_dev);
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return rc;
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}
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static struct pci_device_id tpm_pci_tbl[] __devinitdata = {
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0)},
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12)},
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0)},
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12)},
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0)},
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{PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_LPC)},
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{0,}
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};
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MODULE_DEVICE_TABLE(pci, tpm_pci_tbl);
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static struct pci_driver nsc_pci_driver = {
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.name = "tpm_nsc",
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.id_table = tpm_pci_tbl,
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.probe = tpm_nsc_init,
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.remove = __devexit_p(tpm_remove),
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.suspend = tpm_pm_suspend,
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.resume = tpm_pm_resume,
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};
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static int __init init_nsc(void)
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{
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return pci_register_driver(&nsc_pci_driver);
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}
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static void __exit cleanup_nsc(void)
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{
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pci_unregister_driver(&nsc_pci_driver);
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}
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module_init(init_nsc);
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module_exit(cleanup_nsc);
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MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)");
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MODULE_DESCRIPTION("TPM Driver");
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MODULE_VERSION("2.0");
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MODULE_LICENSE("GPL");
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