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6a12235c7d
There seems to be no reason for these -- they're a 1:1 mapping on all platforms. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
32 lines
1.0 KiB
C
32 lines
1.0 KiB
C
#ifndef _ASM_X86_AGP_H
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#define _ASM_X86_AGP_H
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#include <asm/pgtable.h>
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#include <asm/cacheflush.h>
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/*
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* Functions to keep the agpgart mappings coherent with the MMU. The
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* GART gives the CPU a physical alias of pages in memory. The alias
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* region is mapped uncacheable. Make sure there are no conflicting
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* mappings with different cachability attributes for the same
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* page. This avoids data corruption on some CPUs.
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*/
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#define map_page_into_agp(page) set_pages_uc(page, 1)
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#define unmap_page_from_agp(page) set_pages_wb(page, 1)
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/*
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* Could use CLFLUSH here if the cpu supports it. But then it would
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* need to be called for each cacheline of the whole page so it may
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* not be worth it. Would need a page for it.
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*/
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#define flush_agp_cache() wbinvd()
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/* GATT allocation. Returns/accepts GATT kernel virtual address. */
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#define alloc_gatt_pages(order) \
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((char *)__get_free_pages(GFP_KERNEL, (order)))
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#define free_gatt_pages(table, order) \
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free_pages((unsigned long)(table), (order))
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#endif /* _ASM_X86_AGP_H */
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