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https://github.com/edk2-porting/linux-next.git
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ccbc6554ed
Change legacy name master to modern name host or controller. No functional changed. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20230110131805.2827248-4-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
834 lines
22 KiB
C
834 lines
22 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Driver for Atmel QSPI Controller
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*
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* Copyright (C) 2015 Atmel Corporation
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* Copyright (C) 2018 Cryptera A/S
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*
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* Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>
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* Author: Piotr Bugalski <bugalski.piotr@gmail.com>
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*
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* This driver is based on drivers/mtd/spi-nor/fsl-quadspi.c from Freescale.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/spi/spi-mem.h>
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/* QSPI register offsets */
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#define QSPI_CR 0x0000 /* Control Register */
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#define QSPI_MR 0x0004 /* Mode Register */
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#define QSPI_RD 0x0008 /* Receive Data Register */
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#define QSPI_TD 0x000c /* Transmit Data Register */
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#define QSPI_SR 0x0010 /* Status Register */
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#define QSPI_IER 0x0014 /* Interrupt Enable Register */
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#define QSPI_IDR 0x0018 /* Interrupt Disable Register */
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#define QSPI_IMR 0x001c /* Interrupt Mask Register */
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#define QSPI_SCR 0x0020 /* Serial Clock Register */
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#define QSPI_IAR 0x0030 /* Instruction Address Register */
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#define QSPI_ICR 0x0034 /* Instruction Code Register */
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#define QSPI_WICR 0x0034 /* Write Instruction Code Register */
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#define QSPI_IFR 0x0038 /* Instruction Frame Register */
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#define QSPI_RICR 0x003C /* Read Instruction Code Register */
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#define QSPI_SMR 0x0040 /* Scrambling Mode Register */
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#define QSPI_SKR 0x0044 /* Scrambling Key Register */
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#define QSPI_WPMR 0x00E4 /* Write Protection Mode Register */
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#define QSPI_WPSR 0x00E8 /* Write Protection Status Register */
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#define QSPI_VERSION 0x00FC /* Version Register */
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/* Bitfields in QSPI_CR (Control Register) */
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#define QSPI_CR_QSPIEN BIT(0)
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#define QSPI_CR_QSPIDIS BIT(1)
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#define QSPI_CR_SWRST BIT(7)
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#define QSPI_CR_LASTXFER BIT(24)
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/* Bitfields in QSPI_MR (Mode Register) */
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#define QSPI_MR_SMM BIT(0)
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#define QSPI_MR_LLB BIT(1)
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#define QSPI_MR_WDRBT BIT(2)
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#define QSPI_MR_SMRM BIT(3)
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#define QSPI_MR_CSMODE_MASK GENMASK(5, 4)
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#define QSPI_MR_CSMODE_NOT_RELOADED (0 << 4)
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#define QSPI_MR_CSMODE_LASTXFER (1 << 4)
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#define QSPI_MR_CSMODE_SYSTEMATICALLY (2 << 4)
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#define QSPI_MR_NBBITS_MASK GENMASK(11, 8)
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#define QSPI_MR_NBBITS(n) ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK)
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#define QSPI_MR_DLYBCT_MASK GENMASK(23, 16)
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#define QSPI_MR_DLYBCT(n) (((n) << 16) & QSPI_MR_DLYBCT_MASK)
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#define QSPI_MR_DLYCS_MASK GENMASK(31, 24)
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#define QSPI_MR_DLYCS(n) (((n) << 24) & QSPI_MR_DLYCS_MASK)
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/* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR */
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#define QSPI_SR_RDRF BIT(0)
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#define QSPI_SR_TDRE BIT(1)
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#define QSPI_SR_TXEMPTY BIT(2)
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#define QSPI_SR_OVRES BIT(3)
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#define QSPI_SR_CSR BIT(8)
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#define QSPI_SR_CSS BIT(9)
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#define QSPI_SR_INSTRE BIT(10)
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#define QSPI_SR_QSPIENS BIT(24)
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#define QSPI_SR_CMD_COMPLETED (QSPI_SR_INSTRE | QSPI_SR_CSR)
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/* Bitfields in QSPI_SCR (Serial Clock Register) */
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#define QSPI_SCR_CPOL BIT(0)
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#define QSPI_SCR_CPHA BIT(1)
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#define QSPI_SCR_SCBR_MASK GENMASK(15, 8)
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#define QSPI_SCR_SCBR(n) (((n) << 8) & QSPI_SCR_SCBR_MASK)
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#define QSPI_SCR_DLYBS_MASK GENMASK(23, 16)
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#define QSPI_SCR_DLYBS(n) (((n) << 16) & QSPI_SCR_DLYBS_MASK)
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/* Bitfields in QSPI_ICR (Read/Write Instruction Code Register) */
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#define QSPI_ICR_INST_MASK GENMASK(7, 0)
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#define QSPI_ICR_INST(inst) (((inst) << 0) & QSPI_ICR_INST_MASK)
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#define QSPI_ICR_OPT_MASK GENMASK(23, 16)
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#define QSPI_ICR_OPT(opt) (((opt) << 16) & QSPI_ICR_OPT_MASK)
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/* Bitfields in QSPI_IFR (Instruction Frame Register) */
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#define QSPI_IFR_WIDTH_MASK GENMASK(2, 0)
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#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0 << 0)
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#define QSPI_IFR_WIDTH_DUAL_OUTPUT (1 << 0)
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#define QSPI_IFR_WIDTH_QUAD_OUTPUT (2 << 0)
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#define QSPI_IFR_WIDTH_DUAL_IO (3 << 0)
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#define QSPI_IFR_WIDTH_QUAD_IO (4 << 0)
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#define QSPI_IFR_WIDTH_DUAL_CMD (5 << 0)
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#define QSPI_IFR_WIDTH_QUAD_CMD (6 << 0)
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#define QSPI_IFR_INSTEN BIT(4)
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#define QSPI_IFR_ADDREN BIT(5)
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#define QSPI_IFR_OPTEN BIT(6)
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#define QSPI_IFR_DATAEN BIT(7)
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#define QSPI_IFR_OPTL_MASK GENMASK(9, 8)
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#define QSPI_IFR_OPTL_1BIT (0 << 8)
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#define QSPI_IFR_OPTL_2BIT (1 << 8)
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#define QSPI_IFR_OPTL_4BIT (2 << 8)
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#define QSPI_IFR_OPTL_8BIT (3 << 8)
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#define QSPI_IFR_ADDRL BIT(10)
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#define QSPI_IFR_TFRTYP_MEM BIT(12)
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#define QSPI_IFR_SAMA5D2_WRITE_TRSFR BIT(13)
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#define QSPI_IFR_CRM BIT(14)
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#define QSPI_IFR_NBDUM_MASK GENMASK(20, 16)
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#define QSPI_IFR_NBDUM(n) (((n) << 16) & QSPI_IFR_NBDUM_MASK)
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#define QSPI_IFR_APBTFRTYP_READ BIT(24) /* Defined in SAM9X60 */
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/* Bitfields in QSPI_SMR (Scrambling Mode Register) */
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#define QSPI_SMR_SCREN BIT(0)
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#define QSPI_SMR_RVDIS BIT(1)
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/* Bitfields in QSPI_WPMR (Write Protection Mode Register) */
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#define QSPI_WPMR_WPEN BIT(0)
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#define QSPI_WPMR_WPKEY_MASK GENMASK(31, 8)
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#define QSPI_WPMR_WPKEY(wpkey) (((wpkey) << 8) & QSPI_WPMR_WPKEY_MASK)
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/* Bitfields in QSPI_WPSR (Write Protection Status Register) */
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#define QSPI_WPSR_WPVS BIT(0)
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#define QSPI_WPSR_WPVSRC_MASK GENMASK(15, 8)
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#define QSPI_WPSR_WPVSRC(src) (((src) << 8) & QSPI_WPSR_WPVSRC)
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struct atmel_qspi_caps {
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bool has_qspick;
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bool has_ricr;
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};
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struct atmel_qspi {
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void __iomem *regs;
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void __iomem *mem;
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struct clk *pclk;
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struct clk *qspick;
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struct platform_device *pdev;
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const struct atmel_qspi_caps *caps;
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resource_size_t mmap_size;
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u32 pending;
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u32 mr;
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u32 scr;
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struct completion cmd_completion;
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};
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struct atmel_qspi_mode {
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u8 cmd_buswidth;
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u8 addr_buswidth;
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u8 data_buswidth;
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u32 config;
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};
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static const struct atmel_qspi_mode atmel_qspi_modes[] = {
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{ 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI },
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{ 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT },
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{ 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT },
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{ 1, 2, 2, QSPI_IFR_WIDTH_DUAL_IO },
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{ 1, 4, 4, QSPI_IFR_WIDTH_QUAD_IO },
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{ 2, 2, 2, QSPI_IFR_WIDTH_DUAL_CMD },
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{ 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD },
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};
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#ifdef VERBOSE_DEBUG
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static const char *atmel_qspi_reg_name(u32 offset, char *tmp, size_t sz)
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{
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switch (offset) {
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case QSPI_CR:
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return "CR";
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case QSPI_MR:
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return "MR";
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case QSPI_RD:
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return "MR";
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case QSPI_TD:
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return "TD";
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case QSPI_SR:
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return "SR";
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case QSPI_IER:
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return "IER";
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case QSPI_IDR:
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return "IDR";
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case QSPI_IMR:
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return "IMR";
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case QSPI_SCR:
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return "SCR";
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case QSPI_IAR:
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return "IAR";
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case QSPI_ICR:
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return "ICR/WICR";
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case QSPI_IFR:
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return "IFR";
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case QSPI_RICR:
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return "RICR";
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case QSPI_SMR:
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return "SMR";
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case QSPI_SKR:
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return "SKR";
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case QSPI_WPMR:
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return "WPMR";
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case QSPI_WPSR:
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return "WPSR";
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case QSPI_VERSION:
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return "VERSION";
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default:
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snprintf(tmp, sz, "0x%02x", offset);
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break;
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}
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return tmp;
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}
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#endif /* VERBOSE_DEBUG */
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static u32 atmel_qspi_read(struct atmel_qspi *aq, u32 offset)
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{
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u32 value = readl_relaxed(aq->regs + offset);
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#ifdef VERBOSE_DEBUG
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char tmp[8];
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dev_vdbg(&aq->pdev->dev, "read 0x%08x from %s\n", value,
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atmel_qspi_reg_name(offset, tmp, sizeof(tmp)));
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#endif /* VERBOSE_DEBUG */
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return value;
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}
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static void atmel_qspi_write(u32 value, struct atmel_qspi *aq, u32 offset)
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{
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#ifdef VERBOSE_DEBUG
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char tmp[8];
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dev_vdbg(&aq->pdev->dev, "write 0x%08x into %s\n", value,
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atmel_qspi_reg_name(offset, tmp, sizeof(tmp)));
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#endif /* VERBOSE_DEBUG */
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writel_relaxed(value, aq->regs + offset);
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}
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static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op,
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const struct atmel_qspi_mode *mode)
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{
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if (op->cmd.buswidth != mode->cmd_buswidth)
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return false;
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if (op->addr.nbytes && op->addr.buswidth != mode->addr_buswidth)
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return false;
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if (op->data.nbytes && op->data.buswidth != mode->data_buswidth)
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return false;
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return true;
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}
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static int atmel_qspi_find_mode(const struct spi_mem_op *op)
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{
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u32 i;
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for (i = 0; i < ARRAY_SIZE(atmel_qspi_modes); i++)
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if (atmel_qspi_is_compatible(op, &atmel_qspi_modes[i]))
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return i;
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return -ENOTSUPP;
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}
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static bool atmel_qspi_supports_op(struct spi_mem *mem,
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const struct spi_mem_op *op)
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{
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if (!spi_mem_default_supports_op(mem, op))
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return false;
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if (atmel_qspi_find_mode(op) < 0)
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return false;
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/* special case not supported by hardware */
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if (op->addr.nbytes == 2 && op->cmd.buswidth != op->addr.buswidth &&
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op->dummy.nbytes == 0)
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return false;
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return true;
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}
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static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
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const struct spi_mem_op *op, u32 *offset)
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{
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u32 iar, icr, ifr;
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u32 dummy_cycles = 0;
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int mode;
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iar = 0;
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icr = QSPI_ICR_INST(op->cmd.opcode);
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ifr = QSPI_IFR_INSTEN;
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mode = atmel_qspi_find_mode(op);
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if (mode < 0)
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return mode;
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ifr |= atmel_qspi_modes[mode].config;
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if (op->dummy.nbytes)
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dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
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/*
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* The controller allows 24 and 32-bit addressing while NAND-flash
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* requires 16-bit long. Handling 8-bit long addresses is done using
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* the option field. For the 16-bit addresses, the workaround depends
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* of the number of requested dummy bits. If there are 8 or more dummy
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* cycles, the address is shifted and sent with the first dummy byte.
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* Otherwise opcode is disabled and the first byte of the address
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* contains the command opcode (works only if the opcode and address
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* use the same buswidth). The limitation is when the 16-bit address is
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* used without enough dummy cycles and the opcode is using a different
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* buswidth than the address.
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*/
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if (op->addr.buswidth) {
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switch (op->addr.nbytes) {
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case 0:
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break;
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case 1:
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ifr |= QSPI_IFR_OPTEN | QSPI_IFR_OPTL_8BIT;
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icr |= QSPI_ICR_OPT(op->addr.val & 0xff);
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break;
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case 2:
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if (dummy_cycles < 8 / op->addr.buswidth) {
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ifr &= ~QSPI_IFR_INSTEN;
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ifr |= QSPI_IFR_ADDREN;
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iar = (op->cmd.opcode << 16) |
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(op->addr.val & 0xffff);
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} else {
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ifr |= QSPI_IFR_ADDREN;
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iar = (op->addr.val << 8) & 0xffffff;
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dummy_cycles -= 8 / op->addr.buswidth;
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}
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break;
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case 3:
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ifr |= QSPI_IFR_ADDREN;
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iar = op->addr.val & 0xffffff;
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break;
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case 4:
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ifr |= QSPI_IFR_ADDREN | QSPI_IFR_ADDRL;
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iar = op->addr.val & 0x7ffffff;
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break;
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default:
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return -ENOTSUPP;
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}
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}
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/* offset of the data access in the QSPI memory space */
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*offset = iar;
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/* Set number of dummy cycles */
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if (dummy_cycles)
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ifr |= QSPI_IFR_NBDUM(dummy_cycles);
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/* Set data enable and data transfer type. */
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if (op->data.nbytes) {
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ifr |= QSPI_IFR_DATAEN;
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if (op->addr.nbytes)
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ifr |= QSPI_IFR_TFRTYP_MEM;
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}
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/*
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* If the QSPI controller is set in regular SPI mode, set it in
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* Serial Memory Mode (SMM).
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*/
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if (aq->mr != QSPI_MR_SMM) {
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atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
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aq->mr = QSPI_MR_SMM;
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}
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/* Clear pending interrupts */
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(void)atmel_qspi_read(aq, QSPI_SR);
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/* Set QSPI Instruction Frame registers. */
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if (op->addr.nbytes && !op->data.nbytes)
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atmel_qspi_write(iar, aq, QSPI_IAR);
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if (aq->caps->has_ricr) {
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if (op->data.dir == SPI_MEM_DATA_IN)
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atmel_qspi_write(icr, aq, QSPI_RICR);
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else
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atmel_qspi_write(icr, aq, QSPI_WICR);
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} else {
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if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
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ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR;
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atmel_qspi_write(icr, aq, QSPI_ICR);
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}
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atmel_qspi_write(ifr, aq, QSPI_IFR);
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return 0;
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}
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static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
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{
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struct atmel_qspi *aq = spi_controller_get_devdata(mem->spi->controller);
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u32 sr, offset;
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int err;
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/*
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* Check if the address exceeds the MMIO window size. An improvement
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* would be to add support for regular SPI mode and fall back to it
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* when the flash memories overrun the controller's memory space.
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*/
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if (op->addr.val + op->data.nbytes > aq->mmap_size)
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return -ENOTSUPP;
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err = pm_runtime_resume_and_get(&aq->pdev->dev);
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if (err < 0)
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return err;
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err = atmel_qspi_set_cfg(aq, op, &offset);
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if (err)
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goto pm_runtime_put;
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/* Skip to the final steps if there is no data */
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if (op->data.nbytes) {
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/* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
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(void)atmel_qspi_read(aq, QSPI_IFR);
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/* Send/Receive data */
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if (op->data.dir == SPI_MEM_DATA_IN)
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memcpy_fromio(op->data.buf.in, aq->mem + offset,
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op->data.nbytes);
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else
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memcpy_toio(aq->mem + offset, op->data.buf.out,
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op->data.nbytes);
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/* Release the chip-select */
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atmel_qspi_write(QSPI_CR_LASTXFER, aq, QSPI_CR);
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}
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/* Poll INSTRuction End status */
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sr = atmel_qspi_read(aq, QSPI_SR);
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if ((sr & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
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goto pm_runtime_put;
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|
|
/* Wait for INSTRuction End interrupt */
|
|
reinit_completion(&aq->cmd_completion);
|
|
aq->pending = sr & QSPI_SR_CMD_COMPLETED;
|
|
atmel_qspi_write(QSPI_SR_CMD_COMPLETED, aq, QSPI_IER);
|
|
if (!wait_for_completion_timeout(&aq->cmd_completion,
|
|
msecs_to_jiffies(1000)))
|
|
err = -ETIMEDOUT;
|
|
atmel_qspi_write(QSPI_SR_CMD_COMPLETED, aq, QSPI_IDR);
|
|
|
|
pm_runtime_put:
|
|
pm_runtime_mark_last_busy(&aq->pdev->dev);
|
|
pm_runtime_put_autosuspend(&aq->pdev->dev);
|
|
return err;
|
|
}
|
|
|
|
static const char *atmel_qspi_get_name(struct spi_mem *spimem)
|
|
{
|
|
return dev_name(spimem->spi->dev.parent);
|
|
}
|
|
|
|
static const struct spi_controller_mem_ops atmel_qspi_mem_ops = {
|
|
.supports_op = atmel_qspi_supports_op,
|
|
.exec_op = atmel_qspi_exec_op,
|
|
.get_name = atmel_qspi_get_name
|
|
};
|
|
|
|
static int atmel_qspi_setup(struct spi_device *spi)
|
|
{
|
|
struct spi_controller *ctrl = spi->controller;
|
|
struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
|
|
unsigned long src_rate;
|
|
u32 scbr;
|
|
int ret;
|
|
|
|
if (ctrl->busy)
|
|
return -EBUSY;
|
|
|
|
if (!spi->max_speed_hz)
|
|
return -EINVAL;
|
|
|
|
src_rate = clk_get_rate(aq->pclk);
|
|
if (!src_rate)
|
|
return -EINVAL;
|
|
|
|
/* Compute the QSPI baudrate */
|
|
scbr = DIV_ROUND_UP(src_rate, spi->max_speed_hz);
|
|
if (scbr > 0)
|
|
scbr--;
|
|
|
|
ret = pm_runtime_resume_and_get(ctrl->dev.parent);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
aq->scr = QSPI_SCR_SCBR(scbr);
|
|
atmel_qspi_write(aq->scr, aq, QSPI_SCR);
|
|
|
|
pm_runtime_mark_last_busy(ctrl->dev.parent);
|
|
pm_runtime_put_autosuspend(ctrl->dev.parent);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int atmel_qspi_set_cs_timing(struct spi_device *spi)
|
|
{
|
|
struct spi_controller *ctrl = spi->controller;
|
|
struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
|
|
unsigned long clk_rate;
|
|
u32 cs_setup;
|
|
int delay;
|
|
int ret;
|
|
|
|
delay = spi_delay_to_ns(&spi->cs_setup, NULL);
|
|
if (delay <= 0)
|
|
return delay;
|
|
|
|
clk_rate = clk_get_rate(aq->pclk);
|
|
if (!clk_rate)
|
|
return -EINVAL;
|
|
|
|
cs_setup = DIV_ROUND_UP((delay * DIV_ROUND_UP(clk_rate, 1000000)),
|
|
1000);
|
|
|
|
ret = pm_runtime_resume_and_get(ctrl->dev.parent);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
aq->scr |= QSPI_SCR_DLYBS(cs_setup);
|
|
atmel_qspi_write(aq->scr, aq, QSPI_SCR);
|
|
|
|
pm_runtime_mark_last_busy(ctrl->dev.parent);
|
|
pm_runtime_put_autosuspend(ctrl->dev.parent);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void atmel_qspi_init(struct atmel_qspi *aq)
|
|
{
|
|
/* Reset the QSPI controller */
|
|
atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR);
|
|
|
|
/* Set the QSPI controller by default in Serial Memory Mode */
|
|
atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
|
|
aq->mr = QSPI_MR_SMM;
|
|
|
|
/* Enable the QSPI controller */
|
|
atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR);
|
|
}
|
|
|
|
static irqreturn_t atmel_qspi_interrupt(int irq, void *dev_id)
|
|
{
|
|
struct atmel_qspi *aq = dev_id;
|
|
u32 status, mask, pending;
|
|
|
|
status = atmel_qspi_read(aq, QSPI_SR);
|
|
mask = atmel_qspi_read(aq, QSPI_IMR);
|
|
pending = status & mask;
|
|
|
|
if (!pending)
|
|
return IRQ_NONE;
|
|
|
|
aq->pending |= pending;
|
|
if ((aq->pending & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
|
|
complete(&aq->cmd_completion);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int atmel_qspi_probe(struct platform_device *pdev)
|
|
{
|
|
struct spi_controller *ctrl;
|
|
struct atmel_qspi *aq;
|
|
struct resource *res;
|
|
int irq, err = 0;
|
|
|
|
ctrl = devm_spi_alloc_host(&pdev->dev, sizeof(*aq));
|
|
if (!ctrl)
|
|
return -ENOMEM;
|
|
|
|
ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD;
|
|
ctrl->setup = atmel_qspi_setup;
|
|
ctrl->set_cs_timing = atmel_qspi_set_cs_timing;
|
|
ctrl->bus_num = -1;
|
|
ctrl->mem_ops = &atmel_qspi_mem_ops;
|
|
ctrl->num_chipselect = 1;
|
|
ctrl->dev.of_node = pdev->dev.of_node;
|
|
platform_set_drvdata(pdev, ctrl);
|
|
|
|
aq = spi_controller_get_devdata(ctrl);
|
|
|
|
init_completion(&aq->cmd_completion);
|
|
aq->pdev = pdev;
|
|
|
|
/* Map the registers */
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
|
|
aq->regs = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(aq->regs)) {
|
|
dev_err(&pdev->dev, "missing registers\n");
|
|
return PTR_ERR(aq->regs);
|
|
}
|
|
|
|
/* Map the AHB memory */
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mmap");
|
|
aq->mem = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(aq->mem)) {
|
|
dev_err(&pdev->dev, "missing AHB memory\n");
|
|
return PTR_ERR(aq->mem);
|
|
}
|
|
|
|
aq->mmap_size = resource_size(res);
|
|
|
|
/* Get the peripheral clock */
|
|
aq->pclk = devm_clk_get(&pdev->dev, "pclk");
|
|
if (IS_ERR(aq->pclk))
|
|
aq->pclk = devm_clk_get(&pdev->dev, NULL);
|
|
|
|
if (IS_ERR(aq->pclk)) {
|
|
dev_err(&pdev->dev, "missing peripheral clock\n");
|
|
return PTR_ERR(aq->pclk);
|
|
}
|
|
|
|
/* Enable the peripheral clock */
|
|
err = clk_prepare_enable(aq->pclk);
|
|
if (err) {
|
|
dev_err(&pdev->dev, "failed to enable the peripheral clock\n");
|
|
return err;
|
|
}
|
|
|
|
aq->caps = of_device_get_match_data(&pdev->dev);
|
|
if (!aq->caps) {
|
|
dev_err(&pdev->dev, "Could not retrieve QSPI caps\n");
|
|
err = -EINVAL;
|
|
goto disable_pclk;
|
|
}
|
|
|
|
if (aq->caps->has_qspick) {
|
|
/* Get the QSPI system clock */
|
|
aq->qspick = devm_clk_get(&pdev->dev, "qspick");
|
|
if (IS_ERR(aq->qspick)) {
|
|
dev_err(&pdev->dev, "missing system clock\n");
|
|
err = PTR_ERR(aq->qspick);
|
|
goto disable_pclk;
|
|
}
|
|
|
|
/* Enable the QSPI system clock */
|
|
err = clk_prepare_enable(aq->qspick);
|
|
if (err) {
|
|
dev_err(&pdev->dev,
|
|
"failed to enable the QSPI system clock\n");
|
|
goto disable_pclk;
|
|
}
|
|
}
|
|
|
|
/* Request the IRQ */
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0) {
|
|
err = irq;
|
|
goto disable_qspick;
|
|
}
|
|
err = devm_request_irq(&pdev->dev, irq, atmel_qspi_interrupt,
|
|
0, dev_name(&pdev->dev), aq);
|
|
if (err)
|
|
goto disable_qspick;
|
|
|
|
pm_runtime_set_autosuspend_delay(&pdev->dev, 500);
|
|
pm_runtime_use_autosuspend(&pdev->dev);
|
|
pm_runtime_set_active(&pdev->dev);
|
|
pm_runtime_enable(&pdev->dev);
|
|
pm_runtime_get_noresume(&pdev->dev);
|
|
|
|
atmel_qspi_init(aq);
|
|
|
|
err = spi_register_controller(ctrl);
|
|
if (err) {
|
|
pm_runtime_put_noidle(&pdev->dev);
|
|
pm_runtime_disable(&pdev->dev);
|
|
pm_runtime_set_suspended(&pdev->dev);
|
|
pm_runtime_dont_use_autosuspend(&pdev->dev);
|
|
goto disable_qspick;
|
|
}
|
|
pm_runtime_mark_last_busy(&pdev->dev);
|
|
pm_runtime_put_autosuspend(&pdev->dev);
|
|
|
|
return 0;
|
|
|
|
disable_qspick:
|
|
clk_disable_unprepare(aq->qspick);
|
|
disable_pclk:
|
|
clk_disable_unprepare(aq->pclk);
|
|
|
|
return err;
|
|
}
|
|
|
|
static int atmel_qspi_remove(struct platform_device *pdev)
|
|
{
|
|
struct spi_controller *ctrl = platform_get_drvdata(pdev);
|
|
struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
|
|
int ret;
|
|
|
|
ret = pm_runtime_resume_and_get(&pdev->dev);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
spi_unregister_controller(ctrl);
|
|
atmel_qspi_write(QSPI_CR_QSPIDIS, aq, QSPI_CR);
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
pm_runtime_put_noidle(&pdev->dev);
|
|
|
|
clk_disable_unprepare(aq->qspick);
|
|
clk_disable_unprepare(aq->pclk);
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused atmel_qspi_suspend(struct device *dev)
|
|
{
|
|
struct spi_controller *ctrl = dev_get_drvdata(dev);
|
|
struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
|
|
int ret;
|
|
|
|
ret = pm_runtime_resume_and_get(dev);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
atmel_qspi_write(QSPI_CR_QSPIDIS, aq, QSPI_CR);
|
|
|
|
pm_runtime_mark_last_busy(dev);
|
|
pm_runtime_force_suspend(dev);
|
|
|
|
clk_unprepare(aq->qspick);
|
|
clk_unprepare(aq->pclk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused atmel_qspi_resume(struct device *dev)
|
|
{
|
|
struct spi_controller *ctrl = dev_get_drvdata(dev);
|
|
struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
|
|
int ret;
|
|
|
|
clk_prepare(aq->pclk);
|
|
clk_prepare(aq->qspick);
|
|
|
|
ret = pm_runtime_force_resume(dev);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
atmel_qspi_init(aq);
|
|
|
|
atmel_qspi_write(aq->scr, aq, QSPI_SCR);
|
|
|
|
pm_runtime_mark_last_busy(dev);
|
|
pm_runtime_put_autosuspend(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused atmel_qspi_runtime_suspend(struct device *dev)
|
|
{
|
|
struct spi_controller *ctrl = dev_get_drvdata(dev);
|
|
struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
|
|
|
|
clk_disable(aq->qspick);
|
|
clk_disable(aq->pclk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused atmel_qspi_runtime_resume(struct device *dev)
|
|
{
|
|
struct spi_controller *ctrl = dev_get_drvdata(dev);
|
|
struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
|
|
int ret;
|
|
|
|
ret = clk_enable(aq->pclk);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return clk_enable(aq->qspick);
|
|
}
|
|
|
|
static const struct dev_pm_ops __maybe_unused atmel_qspi_pm_ops = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(atmel_qspi_suspend, atmel_qspi_resume)
|
|
SET_RUNTIME_PM_OPS(atmel_qspi_runtime_suspend,
|
|
atmel_qspi_runtime_resume, NULL)
|
|
};
|
|
|
|
static const struct atmel_qspi_caps atmel_sama5d2_qspi_caps = {};
|
|
|
|
static const struct atmel_qspi_caps atmel_sam9x60_qspi_caps = {
|
|
.has_qspick = true,
|
|
.has_ricr = true,
|
|
};
|
|
|
|
static const struct of_device_id atmel_qspi_dt_ids[] = {
|
|
{
|
|
.compatible = "atmel,sama5d2-qspi",
|
|
.data = &atmel_sama5d2_qspi_caps,
|
|
},
|
|
{
|
|
.compatible = "microchip,sam9x60-qspi",
|
|
.data = &atmel_sam9x60_qspi_caps,
|
|
},
|
|
{ /* sentinel */ }
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, atmel_qspi_dt_ids);
|
|
|
|
static struct platform_driver atmel_qspi_driver = {
|
|
.driver = {
|
|
.name = "atmel_qspi",
|
|
.of_match_table = atmel_qspi_dt_ids,
|
|
.pm = pm_ptr(&atmel_qspi_pm_ops),
|
|
},
|
|
.probe = atmel_qspi_probe,
|
|
.remove = atmel_qspi_remove,
|
|
};
|
|
module_platform_driver(atmel_qspi_driver);
|
|
|
|
MODULE_AUTHOR("Cyrille Pitchen <cyrille.pitchen@atmel.com>");
|
|
MODULE_AUTHOR("Piotr Bugalski <bugalski.piotr@gmail.com");
|
|
MODULE_DESCRIPTION("Atmel QSPI Controller driver");
|
|
MODULE_LICENSE("GPL v2");
|