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2fc0a509e4
Add all supported clocks exported from every susbystem found on MT7622 SoC such as topckgen, apmixedsys, infracfg, pericfg , pciessys, ssusbsys, ethsys and audsys. Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
196 lines
6.3 KiB
C
196 lines
6.3 KiB
C
/*
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* Copyright (c) 2017 MediaTek Inc.
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* Author: Chen Zhong <chen.zhong@mediatek.com>
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* Sean Wang <sean.wang@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include <dt-bindings/clock/mt7622-clk.h>
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#define GATE_AUDIO0(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &audio0_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_no_setclr, \
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}
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#define GATE_AUDIO1(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &audio1_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_no_setclr, \
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}
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#define GATE_AUDIO2(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &audio2_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_no_setclr, \
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}
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#define GATE_AUDIO3(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &audio3_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_no_setclr, \
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}
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static const struct mtk_gate_regs audio0_cg_regs = {
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.set_ofs = 0x0,
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.clr_ofs = 0x0,
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.sta_ofs = 0x0,
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};
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static const struct mtk_gate_regs audio1_cg_regs = {
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.set_ofs = 0x10,
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.clr_ofs = 0x10,
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.sta_ofs = 0x10,
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};
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static const struct mtk_gate_regs audio2_cg_regs = {
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.set_ofs = 0x14,
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.clr_ofs = 0x14,
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.sta_ofs = 0x14,
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};
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static const struct mtk_gate_regs audio3_cg_regs = {
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.set_ofs = 0x634,
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.clr_ofs = 0x634,
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.sta_ofs = 0x634,
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};
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static const struct mtk_gate audio_clks[] = {
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/* AUDIO0 */
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GATE_AUDIO0(CLK_AUDIO_AFE, "audio_afe", "rtc", 2),
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GATE_AUDIO0(CLK_AUDIO_HDMI, "audio_hdmi", "apll1_ck_sel", 20),
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GATE_AUDIO0(CLK_AUDIO_SPDF, "audio_spdf", "apll1_ck_sel", 21),
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GATE_AUDIO0(CLK_AUDIO_APLL, "audio_apll", "apll1_ck_sel", 23),
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/* AUDIO1 */
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GATE_AUDIO1(CLK_AUDIO_I2SIN1, "audio_i2sin1", "a1sys_hp_sel", 0),
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GATE_AUDIO1(CLK_AUDIO_I2SIN2, "audio_i2sin2", "a1sys_hp_sel", 1),
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GATE_AUDIO1(CLK_AUDIO_I2SIN3, "audio_i2sin3", "a1sys_hp_sel", 2),
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GATE_AUDIO1(CLK_AUDIO_I2SIN4, "audio_i2sin4", "a1sys_hp_sel", 3),
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GATE_AUDIO1(CLK_AUDIO_I2SO1, "audio_i2so1", "a1sys_hp_sel", 6),
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GATE_AUDIO1(CLK_AUDIO_I2SO2, "audio_i2so2", "a1sys_hp_sel", 7),
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GATE_AUDIO1(CLK_AUDIO_I2SO3, "audio_i2so3", "a1sys_hp_sel", 8),
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GATE_AUDIO1(CLK_AUDIO_I2SO4, "audio_i2so4", "a1sys_hp_sel", 9),
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GATE_AUDIO1(CLK_AUDIO_ASRCI1, "audio_asrci1", "asm_h_sel", 12),
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GATE_AUDIO1(CLK_AUDIO_ASRCI2, "audio_asrci2", "asm_h_sel", 13),
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GATE_AUDIO1(CLK_AUDIO_ASRCO1, "audio_asrco1", "asm_h_sel", 14),
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GATE_AUDIO1(CLK_AUDIO_ASRCO2, "audio_asrco2", "asm_h_sel", 15),
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GATE_AUDIO1(CLK_AUDIO_INTDIR, "audio_intdir", "intdir_sel", 20),
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GATE_AUDIO1(CLK_AUDIO_A1SYS, "audio_a1sys", "a1sys_hp_sel", 21),
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GATE_AUDIO1(CLK_AUDIO_A2SYS, "audio_a2sys", "a2sys_hp_sel", 22),
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/* AUDIO2 */
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GATE_AUDIO2(CLK_AUDIO_UL1, "audio_ul1", "a1sys_hp_sel", 0),
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GATE_AUDIO2(CLK_AUDIO_UL2, "audio_ul2", "a1sys_hp_sel", 1),
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GATE_AUDIO2(CLK_AUDIO_UL3, "audio_ul3", "a1sys_hp_sel", 2),
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GATE_AUDIO2(CLK_AUDIO_UL4, "audio_ul4", "a1sys_hp_sel", 3),
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GATE_AUDIO2(CLK_AUDIO_UL5, "audio_ul5", "a1sys_hp_sel", 4),
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GATE_AUDIO2(CLK_AUDIO_UL6, "audio_ul6", "a1sys_hp_sel", 5),
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GATE_AUDIO2(CLK_AUDIO_DL1, "audio_dl1", "a1sys_hp_sel", 6),
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GATE_AUDIO2(CLK_AUDIO_DL2, "audio_dl2", "a1sys_hp_sel", 7),
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GATE_AUDIO2(CLK_AUDIO_DL3, "audio_dl3", "a1sys_hp_sel", 8),
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GATE_AUDIO2(CLK_AUDIO_DL4, "audio_dl4", "a1sys_hp_sel", 9),
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GATE_AUDIO2(CLK_AUDIO_DL5, "audio_dl5", "a1sys_hp_sel", 10),
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GATE_AUDIO2(CLK_AUDIO_DL6, "audio_dl6", "a1sys_hp_sel", 11),
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GATE_AUDIO2(CLK_AUDIO_DLMCH, "audio_dlmch", "a1sys_hp_sel", 12),
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GATE_AUDIO2(CLK_AUDIO_ARB1, "audio_arb1", "a1sys_hp_sel", 13),
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GATE_AUDIO2(CLK_AUDIO_AWB, "audio_awb", "a1sys_hp_sel", 14),
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GATE_AUDIO2(CLK_AUDIO_AWB2, "audio_awb2", "a1sys_hp_sel", 15),
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GATE_AUDIO2(CLK_AUDIO_DAI, "audio_dai", "a1sys_hp_sel", 16),
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GATE_AUDIO2(CLK_AUDIO_MOD, "audio_mod", "a1sys_hp_sel", 17),
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/* AUDIO3 */
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GATE_AUDIO3(CLK_AUDIO_ASRCI3, "audio_asrci3", "asm_h_sel", 2),
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GATE_AUDIO3(CLK_AUDIO_ASRCI4, "audio_asrci4", "asm_h_sel", 3),
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GATE_AUDIO3(CLK_AUDIO_ASRCO3, "audio_asrco3", "asm_h_sel", 6),
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GATE_AUDIO3(CLK_AUDIO_ASRCO4, "audio_asrco4", "asm_h_sel", 7),
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GATE_AUDIO3(CLK_AUDIO_MEM_ASRC1, "audio_mem_asrc1", "asm_h_sel", 10),
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GATE_AUDIO3(CLK_AUDIO_MEM_ASRC2, "audio_mem_asrc2", "asm_h_sel", 11),
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GATE_AUDIO3(CLK_AUDIO_MEM_ASRC3, "audio_mem_asrc3", "asm_h_sel", 12),
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GATE_AUDIO3(CLK_AUDIO_MEM_ASRC4, "audio_mem_asrc4", "asm_h_sel", 13),
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GATE_AUDIO3(CLK_AUDIO_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14),
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};
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static int clk_mt7622_audiosys_init(struct platform_device *pdev)
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{
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struct clk_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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int r;
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clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
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mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
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clk_data);
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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if (r)
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dev_err(&pdev->dev,
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"could not register clock provider: %s: %d\n",
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pdev->name, r);
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return r;
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}
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static const struct of_device_id of_match_clk_mt7622_aud[] = {
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{
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.compatible = "mediatek,mt7622-audsys",
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.data = clk_mt7622_audiosys_init,
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}, {
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/* sentinel */
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}
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};
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static int clk_mt7622_aud_probe(struct platform_device *pdev)
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{
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int (*clk_init)(struct platform_device *);
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int r;
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clk_init = of_device_get_match_data(&pdev->dev);
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if (!clk_init)
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return -EINVAL;
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r = clk_init(pdev);
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if (r)
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dev_err(&pdev->dev,
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"could not register clock provider: %s: %d\n",
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pdev->name, r);
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return r;
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}
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static struct platform_driver clk_mt7622_aud_drv = {
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.probe = clk_mt7622_aud_probe,
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.driver = {
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.name = "clk-mt7622-aud",
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.of_match_table = of_match_clk_mt7622_aud,
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},
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};
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builtin_platform_driver(clk_mt7622_aud_drv);
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