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210d53507e
Small changes to register retrieval and order as per latest firmware specification. Signed-off-by: Andrew Vasquez <andrew.vasquez@qlogic.com> Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
260 lines
7.0 KiB
C
260 lines
7.0 KiB
C
/*
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* QLogic Fibre Channel HBA Driver
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* Copyright (c) 2003-2005 QLogic Corporation
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*
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* See LICENSE.qla2xxx for copyright and licensing details.
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*/
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/*
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* Driver debug definitions.
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*/
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/* #define QL_DEBUG_LEVEL_1 */ /* Output register accesses to COM1 */
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/* #define QL_DEBUG_LEVEL_2 */ /* Output error msgs to COM1 */
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/* #define QL_DEBUG_LEVEL_3 */ /* Output function trace msgs to COM1 */
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/* #define QL_DEBUG_LEVEL_4 */ /* Output NVRAM trace msgs to COM1 */
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/* #define QL_DEBUG_LEVEL_5 */ /* Output ring trace msgs to COM1 */
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/* #define QL_DEBUG_LEVEL_6 */ /* Output WATCHDOG timer trace to COM1 */
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/* #define QL_DEBUG_LEVEL_7 */ /* Output RISC load trace msgs to COM1 */
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/* #define QL_DEBUG_LEVEL_8 */ /* Output ring saturation msgs to COM1 */
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/* #define QL_DEBUG_LEVEL_9 */ /* Output IOCTL trace msgs */
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/* #define QL_DEBUG_LEVEL_10 */ /* Output IOCTL error msgs */
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/* #define QL_DEBUG_LEVEL_11 */ /* Output Mbx Cmd trace msgs */
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/* #define QL_DEBUG_LEVEL_12 */ /* Output IP trace msgs */
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/* #define QL_DEBUG_LEVEL_13 */ /* Output fdmi function trace msgs */
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/* #define QL_DEBUG_LEVEL_14 */ /* Output RSCN trace msgs */
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/*
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* Local Macro Definitions.
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*/
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#if defined(QL_DEBUG_LEVEL_1) || defined(QL_DEBUG_LEVEL_2) || \
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defined(QL_DEBUG_LEVEL_3) || defined(QL_DEBUG_LEVEL_4) || \
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defined(QL_DEBUG_LEVEL_5) || defined(QL_DEBUG_LEVEL_6) || \
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defined(QL_DEBUG_LEVEL_7) || defined(QL_DEBUG_LEVEL_8) || \
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defined(QL_DEBUG_LEVEL_9) || defined(QL_DEBUG_LEVEL_10) || \
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defined(QL_DEBUG_LEVEL_11) || defined(QL_DEBUG_LEVEL_12) || \
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defined(QL_DEBUG_LEVEL_13) || defined(QL_DEBUG_LEVEL_14)
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#define QL_DEBUG_ROUTINES
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#endif
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/*
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* Macros use for debugging the driver.
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*/
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#undef ENTER_TRACE
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#if defined(ENTER_TRACE)
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#define ENTER(x) do { printk("qla2100 : Entering %s()\n", x); } while (0)
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#define LEAVE(x) do { printk("qla2100 : Leaving %s()\n", x); } while (0)
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#define ENTER_INTR(x) do { printk("qla2100 : Entering %s()\n", x); } while (0)
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#define LEAVE_INTR(x) do { printk("qla2100 : Leaving %s()\n", x); } while (0)
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#else
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#define ENTER(x) do {} while (0)
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#define LEAVE(x) do {} while (0)
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#define ENTER_INTR(x) do {} while (0)
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#define LEAVE_INTR(x) do {} while (0)
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#endif
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#if DEBUG_QLA2100
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#define DEBUG(x) do {x;} while (0);
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#else
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#define DEBUG(x) do {} while (0);
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#endif
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#if defined(QL_DEBUG_LEVEL_1)
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#define DEBUG1(x) do {x;} while (0);
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#else
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#define DEBUG1(x) do {} while (0);
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#endif
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#if defined(QL_DEBUG_LEVEL_2)
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#define DEBUG2(x) do {x;} while (0);
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#define DEBUG2_3(x) do {x;} while (0);
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#define DEBUG2_3_11(x) do {x;} while (0);
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#define DEBUG2_9_10(x) do {x;} while (0);
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#define DEBUG2_11(x) do {x;} while (0);
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#define DEBUG2_13(x) do {x;} while (0);
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#else
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#define DEBUG2(x) do {} while (0);
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#endif
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#if defined(QL_DEBUG_LEVEL_3)
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#define DEBUG3(x) do {x;} while (0);
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#define DEBUG2_3(x) do {x;} while (0);
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#define DEBUG2_3_11(x) do {x;} while (0);
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#define DEBUG3_11(x) do {x;} while (0);
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#else
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#define DEBUG3(x) do {} while (0);
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#if !defined(QL_DEBUG_LEVEL_2)
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#define DEBUG2_3(x) do {} while (0);
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#endif
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#endif
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#if defined(QL_DEBUG_LEVEL_4)
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#define DEBUG4(x) do {x;} while (0);
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#else
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#define DEBUG4(x) do {} while (0);
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#endif
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#if defined(QL_DEBUG_LEVEL_5)
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#define DEBUG5(x) do {x;} while (0);
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#else
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#define DEBUG5(x) do {} while (0);
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#endif
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#if defined(QL_DEBUG_LEVEL_7)
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#define DEBUG7(x) do {x;} while (0);
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#else
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#define DEBUG7(x) do {} while (0);
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#endif
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#if defined(QL_DEBUG_LEVEL_9)
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#define DEBUG9(x) do {x;} while (0);
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#define DEBUG9_10(x) do {x;} while (0);
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#define DEBUG2_9_10(x) do {x;} while (0);
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#else
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#define DEBUG9(x) do {} while (0);
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#endif
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#if defined(QL_DEBUG_LEVEL_10)
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#define DEBUG10(x) do {x;} while (0);
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#define DEBUG2_9_10(x) do {x;} while (0);
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#define DEBUG9_10(x) do {x;} while (0);
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#else
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#define DEBUG10(x) do {} while (0);
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#if !defined(DEBUG2_9_10)
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#define DEBUG2_9_10(x) do {} while (0);
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#endif
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#if !defined(DEBUG9_10)
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#define DEBUG9_10(x) do {} while (0);
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#endif
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#endif
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#if defined(QL_DEBUG_LEVEL_11)
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#define DEBUG11(x) do{x;} while(0);
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#if !defined(DEBUG2_11)
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#define DEBUG2_11(x) do{x;} while(0);
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#endif
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#if !defined(DEBUG2_3_11)
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#define DEBUG2_3_11(x) do{x;} while(0);
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#endif
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#if !defined(DEBUG3_11)
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#define DEBUG3_11(x) do{x;} while(0);
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#endif
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#else
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#define DEBUG11(x) do{} while(0);
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#if !defined(QL_DEBUG_LEVEL_2)
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#define DEBUG2_11(x) do{} while(0);
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#if !defined(QL_DEBUG_LEVEL_3)
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#define DEBUG2_3_11(x) do{} while(0);
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#endif
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#endif
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#if !defined(QL_DEBUG_LEVEL_3)
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#define DEBUG3_11(x) do{} while(0);
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#endif
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#endif
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#if defined(QL_DEBUG_LEVEL_12)
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#define DEBUG12(x) do {x;} while (0);
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#else
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#define DEBUG12(x) do {} while (0);
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#endif
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#if defined(QL_DEBUG_LEVEL_13)
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#define DEBUG13(x) do {x;} while (0)
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#if !defined(DEBUG2_13)
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#define DEBUG2_13(x) do {x;} while(0)
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#endif
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#else
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#define DEBUG13(x) do {} while (0)
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#if !defined(QL_DEBUG_LEVEL_2)
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#define DEBUG2_13(x) do {} while(0)
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#endif
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#endif
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#if defined(QL_DEBUG_LEVEL_14)
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#define DEBUG14(x) do {x;} while (0)
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#else
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#define DEBUG14(x) do {} while (0)
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#endif
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/*
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* Firmware Dump structure definition
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*/
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#define FW_DUMP_SIZE_128K 0xBC000
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#define FW_DUMP_SIZE_512K 0x2FC000
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#define FW_DUMP_SIZE_1M 0x5FC000
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struct qla2300_fw_dump {
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uint16_t hccr;
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uint16_t pbiu_reg[8];
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uint16_t risc_host_reg[8];
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uint16_t mailbox_reg[32];
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uint16_t resp_dma_reg[32];
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uint16_t dma_reg[48];
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uint16_t risc_hdw_reg[16];
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uint16_t risc_gp0_reg[16];
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uint16_t risc_gp1_reg[16];
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uint16_t risc_gp2_reg[16];
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uint16_t risc_gp3_reg[16];
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uint16_t risc_gp4_reg[16];
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uint16_t risc_gp5_reg[16];
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uint16_t risc_gp6_reg[16];
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uint16_t risc_gp7_reg[16];
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uint16_t frame_buf_hdw_reg[64];
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uint16_t fpm_b0_reg[64];
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uint16_t fpm_b1_reg[64];
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uint16_t risc_ram[0xf800];
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uint16_t stack_ram[0x1000];
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uint16_t data_ram[1];
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};
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struct qla2100_fw_dump {
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uint16_t hccr;
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uint16_t pbiu_reg[8];
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uint16_t mailbox_reg[32];
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uint16_t dma_reg[48];
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uint16_t risc_hdw_reg[16];
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uint16_t risc_gp0_reg[16];
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uint16_t risc_gp1_reg[16];
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uint16_t risc_gp2_reg[16];
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uint16_t risc_gp3_reg[16];
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uint16_t risc_gp4_reg[16];
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uint16_t risc_gp5_reg[16];
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uint16_t risc_gp6_reg[16];
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uint16_t risc_gp7_reg[16];
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uint16_t frame_buf_hdw_reg[16];
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uint16_t fpm_b0_reg[64];
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uint16_t fpm_b1_reg[64];
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uint16_t risc_ram[0xf000];
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};
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#define FW_DUMP_SIZE_24XX 0x2B0000
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struct qla24xx_fw_dump {
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uint32_t host_status;
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uint32_t host_reg[32];
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uint32_t shadow_reg[7];
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uint16_t mailbox_reg[32];
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uint32_t xseq_gp_reg[128];
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uint32_t xseq_0_reg[16];
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uint32_t xseq_1_reg[16];
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uint32_t rseq_gp_reg[128];
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uint32_t rseq_0_reg[16];
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uint32_t rseq_1_reg[16];
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uint32_t rseq_2_reg[16];
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uint32_t cmd_dma_reg[16];
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uint32_t req0_dma_reg[15];
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uint32_t resp0_dma_reg[15];
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uint32_t req1_dma_reg[15];
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uint32_t xmt0_dma_reg[32];
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uint32_t xmt1_dma_reg[32];
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uint32_t xmt2_dma_reg[32];
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uint32_t xmt3_dma_reg[32];
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uint32_t xmt4_dma_reg[32];
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uint32_t xmt_data_dma_reg[16];
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uint32_t rcvt0_data_dma_reg[32];
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uint32_t rcvt1_data_dma_reg[32];
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uint32_t risc_gp_reg[128];
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uint32_t lmc_reg[112];
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uint32_t fpm_hdw_reg[192];
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uint32_t fb_hdw_reg[176];
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uint32_t code_ram[0x2000];
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uint32_t ext_mem[1];
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};
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