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https://github.com/edk2-porting/linux-next.git
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cf0d19fb30
add simple-bus compatible property to soc nodes for 83xx/85xx platforms
that were missing them. Add same to platform probe code.
This fixes SoC device drivers (such as talitos) to succeed in matching
devices present in the soc node.
also update mpc836x_rdk dts to new SEC bindings (overlooked in commit
3fd4473: powerpc/fsl: update crypto node definition and device tree
instances).
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
266 lines
6.7 KiB
C
266 lines
6.7 KiB
C
/*
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* MPC85xx setup and early boot code plus other random bits.
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*
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* Maintained by Kumar Gala (see MAINTAINERS for contact information)
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*
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* Copyright 2005 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/kdev_t.h>
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#include <linux/delay.h>
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#include <linux/seq_file.h>
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#include <linux/of_platform.h>
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#include <asm/system.h>
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#include <asm/time.h>
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#include <asm/machdep.h>
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#include <asm/pci-bridge.h>
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#include <asm/mpic.h>
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#include <mm/mmu_decl.h>
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#include <asm/udbg.h>
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#include <sysdev/fsl_soc.h>
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#include <sysdev/fsl_pci.h>
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#ifdef CONFIG_CPM2
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#include <asm/cpm2.h>
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#include <sysdev/cpm2_pic.h>
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#endif
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#ifdef CONFIG_PCI
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static int mpc85xx_exclude_device(struct pci_controller *hose,
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u_char bus, u_char devfn)
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{
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if (bus == 0 && PCI_SLOT(devfn) == 0)
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return PCIBIOS_DEVICE_NOT_FOUND;
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else
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return PCIBIOS_SUCCESSFUL;
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}
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#endif /* CONFIG_PCI */
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#ifdef CONFIG_CPM2
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static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
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{
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int cascade_irq;
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while ((cascade_irq = cpm2_get_irq()) >= 0)
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generic_handle_irq(cascade_irq);
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desc->chip->eoi(irq);
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}
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#endif /* CONFIG_CPM2 */
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static void __init mpc85xx_ads_pic_init(void)
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{
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struct mpic *mpic;
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struct resource r;
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struct device_node *np = NULL;
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#ifdef CONFIG_CPM2
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int irq;
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#endif
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np = of_find_node_by_type(np, "open-pic");
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if (!np) {
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printk(KERN_ERR "Could not find open-pic node\n");
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return;
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}
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if (of_address_to_resource(np, 0, &r)) {
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printk(KERN_ERR "Could not map mpic register space\n");
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of_node_put(np);
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return;
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}
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mpic = mpic_alloc(np, r.start,
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MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
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0, 256, " OpenPIC ");
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BUG_ON(mpic == NULL);
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of_node_put(np);
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mpic_init(mpic);
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#ifdef CONFIG_CPM2
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/* Setup CPM2 PIC */
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np = of_find_compatible_node(NULL, NULL, "fsl,cpm2-pic");
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if (np == NULL) {
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printk(KERN_ERR "PIC init: can not find fsl,cpm2-pic node\n");
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return;
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}
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irq = irq_of_parse_and_map(np, 0);
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cpm2_pic_init(np);
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of_node_put(np);
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set_irq_chained_handler(irq, cpm2_cascade);
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#endif
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}
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/*
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* Setup the architecture
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*/
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#ifdef CONFIG_CPM2
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struct cpm_pin {
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int port, pin, flags;
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};
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static const struct cpm_pin mpc8560_ads_pins[] = {
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/* SCC1 */
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{3, 29, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
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{3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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/* SCC2 */
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{2, 12, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{2, 13, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{3, 26, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{3, 27, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{3, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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/* FCC2 */
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{1, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 20, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 22, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{1, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{1, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{1, 25, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{1, 26, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
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{1, 30, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 31, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{2, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK14 */
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{2, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK13 */
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/* FCC3 */
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{1, 4, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{1, 5, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{1, 6, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{1, 8, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 9, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 10, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 11, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 12, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 13, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 14, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{1, 15, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{1, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{2, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK16 */
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{2, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK15 */
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{2, 27, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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};
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static void __init init_ioports(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(mpc8560_ads_pins); i++) {
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const struct cpm_pin *pin = &mpc8560_ads_pins[i];
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cpm2_set_pin(pin->port, pin->pin, pin->flags);
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}
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cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX);
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cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX);
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cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_RX);
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cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_TX);
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cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK13, CPM_CLK_RX);
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cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX);
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cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK15, CPM_CLK_RX);
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cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK16, CPM_CLK_TX);
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}
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#endif
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static void __init mpc85xx_ads_setup_arch(void)
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{
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#ifdef CONFIG_PCI
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struct device_node *np;
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#endif
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if (ppc_md.progress)
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ppc_md.progress("mpc85xx_ads_setup_arch()", 0);
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#ifdef CONFIG_CPM2
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cpm2_reset();
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init_ioports();
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#endif
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#ifdef CONFIG_PCI
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for_each_compatible_node(np, "pci", "fsl,mpc8540-pci")
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fsl_add_bridge(np, 1);
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ppc_md.pci_exclude_device = mpc85xx_exclude_device;
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#endif
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}
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static void mpc85xx_ads_show_cpuinfo(struct seq_file *m)
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{
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uint pvid, svid, phid1;
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uint memsize = total_memory;
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pvid = mfspr(SPRN_PVR);
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svid = mfspr(SPRN_SVR);
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seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
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seq_printf(m, "Machine\t\t: mpc85xx\n");
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seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
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seq_printf(m, "SVR\t\t: 0x%x\n", svid);
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/* Display cpu Pll setting */
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phid1 = mfspr(SPRN_HID1);
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seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
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/* Display the amount of memory */
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seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
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}
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static struct of_device_id __initdata of_bus_ids[] = {
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{ .name = "soc", },
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{ .type = "soc", },
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{ .name = "cpm", },
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{ .name = "localbus", },
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{ .compatible = "simple-bus", },
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{},
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};
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static int __init declare_of_platform_devices(void)
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{
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of_platform_bus_probe(NULL, of_bus_ids, NULL);
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return 0;
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}
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machine_device_initcall(mpc85xx_ads, declare_of_platform_devices);
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/*
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* Called very early, device-tree isn't unflattened
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*/
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static int __init mpc85xx_ads_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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return of_flat_dt_is_compatible(root, "MPC85xxADS");
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}
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define_machine(mpc85xx_ads) {
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.name = "MPC85xx ADS",
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.probe = mpc85xx_ads_probe,
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.setup_arch = mpc85xx_ads_setup_arch,
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.init_IRQ = mpc85xx_ads_pic_init,
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.show_cpuinfo = mpc85xx_ads_show_cpuinfo,
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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};
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