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6d1c244803
As usual, the bulk of this release is again DT file contents. There's a huge number of changes here, and it's challenging to give a crisp overview of just what is in here. To start with: New boards: - TI-based DM3730 from LogicPD (Torpedo) - Cosmic+ M4 (nommu) initial support (Freescale Vybrid) - Raspberry Pi 2 DT files - Watchdog on Meson8b - Veyron-mickey (ASUS Chromebit) DTS - Rockchip rk3228 SoC and eval board - Sigma Designs Tango4 Improvements: - Improved support for Qualcomm APQ8084, including Sony Xperia Z DT files - Misc new devices for Rockchip rk3036 and rk3288 - Allwinner updates for misc SoCs and systems ... and a _large_ number of other changes across the field. Devices added to SoC DTSI and board DTS files for a number of SoC vendors, new product boards on already-supported SoCs, cleanups and refactorings of existing DTS/DTSI files and a bunch of other changes. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJWnr6fAAoJEIwa5zzehBx3p+gP+wYLUqXjCYgyu6oJPxJbWghj gPc4QJmhVlAWTqvE7Ut7RumWzGa7nUEH2QF9tiCLbDAw8727HJXhRHknFwaCsX45 BsvFQaKY99ClfUhoSI9GRa8e2jEArjzEPqkynHW/8FM20qWaj/Z8DDfixG75gR8u onrMw6kprNGwmyQwqu5zLDXhUBCQIs1xRRSabUjV1P5420dbBaGgtmQrdj7k+JDt wo9SKiG6d9CSYil3r7BC+0JwzbKNBxRGs2vv1BJOfbZ3Lj+uC0vj1AxoF/p7dOHy ohuvt7UwwtoUzzFMcMUo7E8qxl9u6bbnPDlUoRF7DVVi5SQoeZd8BOZXOdLRN2OQ qtgsmziDxtvh7Ydj6i89D69x7+GurAFcP8Aturprc5Zd5lO70PAYBD379IhIZ8y1 MVJltIEeuUZo7BaVBCHWQY9jJRtI3bAU6JdFPrFROsuo810IYd72Wbb1ZCfF7SV7 nBRvV7e71VQxb48c3p8Et5FntHuXfUlhkMrQ7Cb+2ugB/diGgZB9NfrZbP3Azv7f A5Ey9tNHaOCUxzYDCw80jTa7OwVWNJf2kOT1yikASk3vODKLv4E5YQ2DULnObWG7 iRmLYuuGka4sMs0ZjpV3kaqs+8rWu08x2rEr5X0wfU+DalIzUWA2oDKSgPLJoacV gXKP039CIxQAiottcppA =XDLa -----END PGP SIGNATURE----- Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM DT updates from Olof Johansson: "As usual, the bulk of this release is again DT file contents. There's a huge number of changes here, and it's challenging to give a crisp overview of just what is in here. To start with: New boards: - TI-based DM3730 from LogicPD (Torpedo) - Cosmic+ M4 (nommu) initial support (Freescale Vybrid) - Raspberry Pi 2 DT files - Watchdog on Meson8b - Veyron-mickey (ASUS Chromebit) DTS - Rockchip rk3228 SoC and eval board - Sigma Designs Tango4 Improvements: - Improved support for Qualcomm APQ8084, including Sony Xperia Z DT files - Misc new devices for Rockchip rk3036 and rk3288 - Allwinner updates for misc SoCs and systems ... and a _large_ number of other changes across the field. Devices added to SoC DTSI and board DTS files for a number of SoC vendors, new product boards on already-supported SoCs, cleanups and refactorings of existing DTS/DTSI files and a bunch of other changes" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (469 commits) ARM: dts: compulab: add new board description ARM: versatile: add the syscon LEDs to the DT dts: vt8500: Fix errors in SDHC node for WM8505 ARM: dts: imx6q: clean up unused ipu2grp ARM: dts: silk: Add compatible property to "partitions" node ARM: dts: gose: Add compatible property to "partitions" node ARM: dts: porter: Add compatible property to "partitions" node ARM: dts: koelsch: Add compatible property to "partitions" node ARM: dts: lager: Add compatible property to "partitions" node ARM: dts: bockw: Add compatible property to "partitions" node ARM: dts: meson8b: Add watchdog node Documentation: watchdog: Add new bindings for meson8b ARM: meson: Add status LED for Odroid-C1 ARM: dts: uniphier: fix a typo in comment block ARM: bcm2835: Add the auxiliary clocks to the device tree. ARM: bcm2835: Add devicetree for bcm2836 and Raspberry Pi 2 B ARM: bcm2835: Move the CPU/peripheral include out of common RPi DT. ARM: bcm2835: Split the DT for peripherals from the DT for the CPU ARM: realview: set up cache correctly on the PB11MPCore ARM: dts: Unify G2D device node with other devices on exynos4 ...
463 lines
11 KiB
Plaintext
463 lines
11 KiB
Plaintext
=================
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ARM CPUs bindings
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=================
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The device tree allows to describe the layout of CPUs in a system through
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the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
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defining properties for every cpu.
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Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:
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https://www.power.org/documentation/epapr-version-1-1/
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with updates for 32-bit and 64-bit ARM systems provided in this document.
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================================
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Convention used in this document
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================================
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This document follows the conventions described in the ePAPR v1.1, with
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the addition:
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- square brackets define bitfields, eg reg[7:0] value of the bitfield in
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the reg property contained in bits 7 down to 0
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=====================================
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cpus and cpu node bindings definition
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=====================================
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The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu
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nodes to be present and contain the properties described below.
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- cpus node
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Description: Container of cpu nodes
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The node name must be "cpus".
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A cpus node must define the following properties:
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- #address-cells
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Usage: required
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Value type: <u32>
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Definition depends on ARM architecture version and
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configuration:
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# On uniprocessor ARM architectures previous to v7
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value must be 1, to enable a simple enumeration
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scheme for processors that do not have a HW CPU
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identification register.
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# On 32-bit ARM 11 MPcore, ARM v7 or later systems
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value must be 1, that corresponds to CPUID/MPIDR
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registers sizes.
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# On ARM v8 64-bit systems value should be set to 2,
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that corresponds to the MPIDR_EL1 register size.
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If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
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in the system, #address-cells can be set to 1, since
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MPIDR_EL1[63:32] bits are not used for CPUs
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identification.
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- #size-cells
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Usage: required
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Value type: <u32>
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Definition: must be set to 0
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- cpu node
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Description: Describes a CPU in an ARM based system
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PROPERTIES
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- device_type
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Usage: required
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Value type: <string>
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Definition: must be "cpu"
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- reg
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Usage and definition depend on ARM architecture version and
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configuration:
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# On uniprocessor ARM architectures previous to v7
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this property is required and must be set to 0.
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# On ARM 11 MPcore based systems this property is
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required and matches the CPUID[11:0] register bits.
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Bits [11:0] in the reg cell must be set to
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bits [11:0] in CPU ID register.
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All other bits in the reg cell must be set to 0.
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# On 32-bit ARM v7 or later systems this property is
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required and matches the CPU MPIDR[23:0] register
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bits.
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Bits [23:0] in the reg cell must be set to
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bits [23:0] in MPIDR.
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All other bits in the reg cell must be set to 0.
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# On ARM v8 64-bit systems this property is required
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and matches the MPIDR_EL1 register affinity bits.
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* If cpus node's #address-cells property is set to 2
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The first reg cell bits [7:0] must be set to
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bits [39:32] of MPIDR_EL1.
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The second reg cell bits [23:0] must be set to
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bits [23:0] of MPIDR_EL1.
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* If cpus node's #address-cells property is set to 1
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The reg cell bits [23:0] must be set to bits [23:0]
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of MPIDR_EL1.
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All other bits in the reg cells must be set to 0.
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- compatible:
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Usage: required
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Value type: <string>
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Definition: should be one of:
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"arm,arm710t"
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"arm,arm720t"
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"arm,arm740t"
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"arm,arm7ej-s"
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"arm,arm7tdmi"
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"arm,arm7tdmi-s"
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"arm,arm9es"
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"arm,arm9ej-s"
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"arm,arm920t"
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"arm,arm922t"
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"arm,arm925"
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"arm,arm926e-s"
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"arm,arm926ej-s"
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"arm,arm940t"
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"arm,arm946e-s"
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"arm,arm966e-s"
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"arm,arm968e-s"
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"arm,arm9tdmi"
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"arm,arm1020e"
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"arm,arm1020t"
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"arm,arm1022e"
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"arm,arm1026ej-s"
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"arm,arm1136j-s"
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"arm,arm1136jf-s"
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"arm,arm1156t2-s"
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"arm,arm1156t2f-s"
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"arm,arm1176jzf"
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"arm,arm1176jz-s"
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"arm,arm1176jzf-s"
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"arm,arm11mpcore"
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"arm,cortex-a5"
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"arm,cortex-a7"
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"arm,cortex-a8"
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"arm,cortex-a9"
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"arm,cortex-a12"
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"arm,cortex-a15"
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"arm,cortex-a17"
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"arm,cortex-a53"
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"arm,cortex-a57"
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"arm,cortex-a72"
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"arm,cortex-m0"
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"arm,cortex-m0+"
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"arm,cortex-m1"
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"arm,cortex-m3"
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"arm,cortex-m4"
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"arm,cortex-r4"
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"arm,cortex-r5"
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"arm,cortex-r7"
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"brcm,brahma-b15"
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"cavium,thunder"
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"faraday,fa526"
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"intel,sa110"
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"intel,sa1100"
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"marvell,feroceon"
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"marvell,mohawk"
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"marvell,pj4a"
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"marvell,pj4b"
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"marvell,sheeva-v5"
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"nvidia,tegra132-denver"
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"qcom,krait"
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"qcom,scorpion"
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- enable-method
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Value type: <stringlist>
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Usage and definition depend on ARM architecture version.
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# On ARM v8 64-bit this property is required and must
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be one of:
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"psci"
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"spin-table"
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# On ARM 32-bit systems this property is optional and
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can be one of:
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"allwinner,sun6i-a31"
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"allwinner,sun8i-a23"
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"arm,psci"
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"arm,realview-smp"
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"brcm,bcm-nsp-smp"
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"brcm,brahma-b15"
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"marvell,armada-375-smp"
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"marvell,armada-380-smp"
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"marvell,armada-390-smp"
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"marvell,armada-xp-smp"
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"mediatek,mt6589-smp"
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"mediatek,mt81xx-tz-smp"
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"qcom,gcc-msm8660"
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"qcom,kpss-acc-v1"
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"qcom,kpss-acc-v2"
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"rockchip,rk3036-smp"
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"rockchip,rk3066-smp"
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"ste,dbx500-smp"
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- cpu-release-addr
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Usage: required for systems that have an "enable-method"
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property value of "spin-table".
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Value type: <prop-encoded-array>
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Definition:
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# On ARM v8 64-bit systems must be a two cell
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property identifying a 64-bit zero-initialised
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memory location.
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- qcom,saw
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Usage: required for systems that have an "enable-method"
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property value of "qcom,kpss-acc-v1" or
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"qcom,kpss-acc-v2"
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Value type: <phandle>
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Definition: Specifies the SAW[1] node associated with this CPU.
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- qcom,acc
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Usage: required for systems that have an "enable-method"
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property value of "qcom,kpss-acc-v1" or
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"qcom,kpss-acc-v2"
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Value type: <phandle>
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Definition: Specifies the ACC[2] node associated with this CPU.
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- cpu-idle-states
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Usage: Optional
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Value type: <prop-encoded-array>
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Definition:
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# List of phandles to idle state nodes supported
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by this cpu [3].
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- rockchip,pmu
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Usage: optional for systems that have an "enable-method"
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property value of "rockchip,rk3066-smp"
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While optional, it is the preferred way to get access to
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the cpu-core power-domains.
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Value type: <phandle>
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Definition: Specifies the syscon node controlling the cpu core
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power domains.
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- dynamic-power-coefficient
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Usage: optional
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Value type: <prop-encoded-array>
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Definition: A u32 value that represents the running time dynamic
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power coefficient in units of mW/MHz/uVolt^2. The
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coefficient can either be calculated from power
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measurements or derived by analysis.
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The dynamic power consumption of the CPU is
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proportional to the square of the Voltage (V) and
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the clock frequency (f). The coefficient is used to
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calculate the dynamic power as below -
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Pdyn = dynamic-power-coefficient * V^2 * f
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where voltage is in uV, frequency is in MHz.
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Example 1 (dual-cluster big.LITTLE system 32-bit):
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cpus {
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#size-cells = <0>;
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#address-cells = <1>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x1>;
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};
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cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x100>;
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};
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cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x101>;
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};
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};
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Example 2 (Cortex-A8 uniprocessor 32-bit system):
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cpus {
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#size-cells = <0>;
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#address-cells = <1>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a8";
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reg = <0x0>;
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};
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};
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Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
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cpus {
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#size-cells = <0>;
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#address-cells = <1>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,arm926ej-s";
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reg = <0x0>;
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};
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};
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Example 4 (ARM Cortex-A57 64-bit system):
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cpus {
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#size-cells = <0>;
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#address-cells = <2>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x0>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x1>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x100>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x101>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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cpu@10000 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x10000>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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cpu@10001 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x10001>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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cpu@10100 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x10100>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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cpu@10101 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x10101>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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cpu@100000000 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x1 0x0>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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cpu@100000001 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x1 0x1>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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cpu@100000100 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x1 0x100>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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cpu@100000101 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x1 0x101>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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cpu@100010000 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x1 0x10000>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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cpu@100010001 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x1 0x10001>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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cpu@100010100 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x1 0x10100>;
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enable-method = "spin-table";
|
|
cpu-release-addr = <0 0x20000000>;
|
|
};
|
|
|
|
cpu@100010101 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a57";
|
|
reg = <0x1 0x10101>;
|
|
enable-method = "spin-table";
|
|
cpu-release-addr = <0 0x20000000>;
|
|
};
|
|
};
|
|
|
|
--
|
|
[1] arm/msm/qcom,saw2.txt
|
|
[2] arm/msm/qcom,kpss-acc.txt
|
|
[3] ARM Linux kernel documentation - idle states bindings
|
|
Documentation/devicetree/bindings/arm/idle-states.txt
|