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This adds the binding documentation for the Imagination Technologies hash accelerator that provides hardware acceleration for SHA1/SHA224/SHA256/MD5 hashes. This hardware will be present in the upcoming pistachio SoC. Signed-off-by: James Hartley <james.hartley@imgtec.com> Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
28 lines
926 B
Plaintext
28 lines
926 B
Plaintext
Imagination Technologies hardware hash accelerator
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The hash accelerator provides hardware hashing acceleration for
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SHA1, SHA224, SHA256 and MD5 hashes
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Required properties:
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- compatible : "img,hash-accelerator"
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- reg : Offset and length of the register set for the module, and the DMA port
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- interrupts : The designated IRQ line for the hashing module.
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- dmas : DMA specifier as per Documentation/devicetree/bindings/dma/dma.txt
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- dma-names : Should be "tx"
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- clocks : Clock specifiers
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- clock-names : "sys" Used to clock the hash block registers
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"hash" Used to clock data through the accelerator
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Example:
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hash: hash@18149600 {
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compatible = "img,hash-accelerator";
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reg = <0x18149600 0x100>, <0x18101100 0x4>;
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interrupts = <GIC_SHARED 59 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma 8 0xffffffff 0>;
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dma-names = "tx";
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clocks = <&cr_periph SYS_CLK_HASH>, <&clk_periph PERIPH_CLK_ROM>;
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clock-names = "sys", "hash";
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};
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