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e65fdfd6ca
There is no need to expose these settings outside the scope of the interrupt controller code itself. Signed-off-by: Sylvain Munaut <tnt@246tNt.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Paul Mackerras <paulus@samba.org>
54 lines
1.4 KiB
C
54 lines
1.4 KiB
C
/*
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* Header file for Freescale MPC52xx Interrupt controller
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*
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* Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com>
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* Copyright (C) 2003 MontaVista, Software, Inc.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#ifndef __POWERPC_SYSDEV_MPC52xx_PIC_H__
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#define __POWERPC_SYSDEV_MPC52xx_PIC_H__
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#include <asm/types.h>
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/* HW IRQ mapping */
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#define MPC52xx_IRQ_L1_CRIT (0)
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#define MPC52xx_IRQ_L1_MAIN (1)
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#define MPC52xx_IRQ_L1_PERP (2)
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#define MPC52xx_IRQ_L1_SDMA (3)
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#define MPC52xx_IRQ_L1_OFFSET (6)
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#define MPC52xx_IRQ_L1_MASK (0x00c0)
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#define MPC52xx_IRQ_L2_OFFSET (0)
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#define MPC52xx_IRQ_L2_MASK (0x003f)
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#define MPC52xx_IRQ_HIGHTESTHWIRQ (0xd0)
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/* Interrupt controller Register set */
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struct mpc52xx_intr {
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u32 per_mask; /* INTR + 0x00 */
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u32 per_pri1; /* INTR + 0x04 */
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u32 per_pri2; /* INTR + 0x08 */
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u32 per_pri3; /* INTR + 0x0c */
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u32 ctrl; /* INTR + 0x10 */
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u32 main_mask; /* INTR + 0x14 */
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u32 main_pri1; /* INTR + 0x18 */
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u32 main_pri2; /* INTR + 0x1c */
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u32 reserved1; /* INTR + 0x20 */
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u32 enc_status; /* INTR + 0x24 */
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u32 crit_status; /* INTR + 0x28 */
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u32 main_status; /* INTR + 0x2c */
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u32 per_status; /* INTR + 0x30 */
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u32 reserved2; /* INTR + 0x34 */
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u32 per_error; /* INTR + 0x38 */
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};
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#endif /* __POWERPC_SYSDEV_MPC52xx_PIC_H__ */
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