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The R8A7779 SoC has several clocks that are too custom to be supported in a generic driver. Those clocks are all fixed rate clocks with multiplier and divisor set according to boot mode configuration. Based on work for R-Car Gen2 SoCs by Laurent Pinchart. Cc: devicetree@vger.kernel.org Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Mike Turquette <mturquette@linaro.org>
28 lines
761 B
Plaintext
28 lines
761 B
Plaintext
* Renesas R8A7779 Clock Pulse Generator (CPG)
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The CPG generates core clocks for the R8A7779. It includes one PLL and
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several fixed ratio dividers
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Required Properties:
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- compatible: Must be "renesas,r8a7779-cpg-clocks"
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- reg: Base address and length of the memory resource used by the CPG
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- clocks: Reference to the parent clock
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- #clock-cells: Must be 1
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- clock-output-names: The names of the clocks. Supported clocks are "plla",
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"z", "zs", "s", "s1", "p", "b", "out".
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Example
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-------
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cpg_clocks: cpg_clocks@ffc80000 {
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compatible = "renesas,r8a7779-cpg-clocks";
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reg = <0 0xffc80000 0 0x30>;
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clocks = <&extal_clk>;
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#clock-cells = <1>;
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clock-output-names = "plla", "z", "zs", "s", "s1", "p",
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"b", "out";
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};
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