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72c5839515
GICv3 introduces new system registers accessible with the full msr/mrs syntax (e.g. mrs x0, Sop0_op1_CRm_CRn_op2). However, only recent binutils understand the new syntax. This patch introduces msr_s/mrs_s assembly macros which generate the equivalent instructions above and converts the existing GICv3 code (both drivers/irqchip/ and arch/arm64/kernel/). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Reported-by: Olof Johansson <olof@lixom.net> Tested-by: Olof Johansson <olof@lixom.net> Suggested-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Jason Cooper <jason@lakedaemon.net> Cc: Will Deacon <will.deacon@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com> |
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.. | ||
arm-gic-v3.h | ||
arm-gic.h | ||
arm-vic.h | ||
chained_irq.h | ||
irq-crossbar.h | ||
metag-ext.h | ||
metag.h | ||
mmp.h | ||
mxs.h | ||
spear-shirq.h | ||
versatile-fpga.h | ||
xtensa-mx.h | ||
xtensa-pic.h |