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e02db0aa3e
This patch fix the problem with rootfs on JFFS2 with early printk console turned on. The origin version used TLB63 for temporary early printk mapping. The code expect that kernel is not able to use all 64 TLB entries till early printk console is remapped by ioremap. After that temporary mapping on TLB63 is silently lost. This expectation give the opportunity to have early console pretty early. Microblaze systems with JFFS2 rootfs with early printk console turned on used more than 64 TLB entries before kernel can remap early console. Based on that kernel does access to bad area because early printk mapping is rewritten. This patch introduces tlb_skip variable which dynamically stores number of skipped TLB entries from the TLB0. skip_tlb=2 means that TLB0 and TLB1 should be skipped. MICROBLAZE_TLB_SKIP defines how many TLB is skipped at the kernel start. They can be used for user purpose. TLB 63 is used for temporary LMB mapping (MICROBLAZE_LMB_TLB_ID). Also clean TLBLO when kernel starts. For specific kernel sizes kernel can use just one TLB. Detect this case and use the second TLB for general purpose. Change _tlbia function to flush TLB entries from tlb_skip to TLB_SIZE. Export tlb_skip size through debugfs. Signed-off-by: Michal Simek <monstr@monstr.eu>
101 lines
2.1 KiB
ArmAsm
101 lines
2.1 KiB
ArmAsm
/*
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* Miscellaneous low-level MMU functions.
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*
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* Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2008-2009 PetaLogix
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* Copyright (C) 2007 Xilinx, Inc. All rights reserved.
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*
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* Derived from arch/ppc/kernel/misc.S
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*/
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#include <linux/linkage.h>
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#include <linux/sys.h>
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#include <asm/unistd.h>
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#include <linux/errno.h>
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#include <asm/mmu.h>
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#include <asm/page.h>
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.text
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/*
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* Flush MMU TLB
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*
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* We avoid flushing the pinned 0, 1 and possibly 2 entries.
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*/
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.globl _tlbia;
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.type _tlbia, @function
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.align 4;
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_tlbia:
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lwi r12, r0, tlb_skip;
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/* isync */
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_tlbia_1:
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mts rtlbx, r12
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nop
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mts rtlbhi, r0 /* flush: ensure V is clear */
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nop
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rsubi r11, r12, MICROBLAZE_TLB_SIZE - 1
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bneid r11, _tlbia_1 /* loop for all entries */
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addik r12, r12, 1
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/* sync */
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rtsd r15, 8
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nop
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.size _tlbia, . - _tlbia
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/*
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* Flush MMU TLB for a particular address (in r5)
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*/
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.globl _tlbie;
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.type _tlbie, @function
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.align 4;
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_tlbie:
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mts rtlbsx, r5 /* look up the address in TLB */
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nop
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mfs r12, rtlbx /* Retrieve index */
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nop
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blti r12, _tlbie_1 /* Check if found */
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mts rtlbhi, r0 /* flush: ensure V is clear */
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nop
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_tlbie_1:
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rtsd r15, 8
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nop
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.size _tlbie, . - _tlbie
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/*
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* Allocate TLB entry for early console
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*/
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.globl early_console_reg_tlb_alloc;
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.type early_console_reg_tlb_alloc, @function
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.align 4;
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early_console_reg_tlb_alloc:
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/*
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* Load a TLB entry for the UART, so that microblaze_progress() can use
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* the UARTs nice and early. We use a 4k real==virtual mapping.
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*/
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lwi r4, r0, tlb_skip
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mts rtlbx, r4 /* TLB slot 63 */
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or r4,r5,r0
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andi r4,r4,0xfffff000
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ori r4,r4,(TLB_WR|TLB_I|TLB_M|TLB_G)
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andi r5,r5,0xfffff000
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ori r5,r5,(TLB_VALID | TLB_PAGESZ(PAGESZ_4K))
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mts rtlblo,r4 /* Load the data portion of the entry */
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nop
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mts rtlbhi,r5 /* Load the tag portion of the entry */
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nop
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lwi r5, r0, tlb_skip
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addik r5, r5, 1
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swi r5, r0, tlb_skip
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rtsd r15, 8
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nop
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.size early_console_reg_tlb_alloc, . - early_console_reg_tlb_alloc
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